diff options
author | Simon Glass <sjg@chromium.org> | 2023-08-21 21:16:56 -0600 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-08-31 13:16:54 -0400 |
commit | f72d0d4a2f9a2d05ebeefb583992cc620f7c4c2d (patch) | |
tree | afaa54f94971d8dc3e9c9b7bb5d860053c37b6eb /arch/x86 | |
parent | dd802467f44b68d6ed9315ffe3002b17dc43b622 (diff) | |
download | u-boot-f72d0d4a2f9a2d05ebeefb583992cc620f7c4c2d.zip u-boot-f72d0d4a2f9a2d05ebeefb583992cc620f7c4c2d.tar.gz u-boot-f72d0d4a2f9a2d05ebeefb583992cc620f7c4c2d.tar.bz2 |
event: Convert existing spy records to simple
Very few of the existing event-spy records use the arguments they are
passed. Update them to use a simple spy instead, to simplify the code.
Where an adaptor function is currently used, remove it where possible.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/cpu/baytrail/cpu.c | 4 | ||||
-rw-r--r-- | arch/x86/cpu/broadwell/cpu.c | 4 | ||||
-rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 4 | ||||
-rw-r--r-- | arch/x86/cpu/quark/quark.c | 26 | ||||
-rw-r--r-- | arch/x86/lib/fsp2/fsp_init.c | 4 |
5 files changed, 18 insertions, 24 deletions
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index 4a7b4f6..c270426 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -45,7 +45,7 @@ static void hsuart_clock_set(void *base) * Configure the internal clock of both SIO HS-UARTs, if they are enabled * via FSP */ -static int baytrail_uart_init(void *ctx, struct event *event) +static int baytrail_uart_init(void) { struct udevice *dev; void *base; @@ -64,7 +64,7 @@ static int baytrail_uart_init(void *ctx, struct event *event) return 0; } -EVENT_SPY(EVT_DM_POST_INIT_F, baytrail_uart_init); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, baytrail_uart_init); static void set_max_freq(void) { diff --git a/arch/x86/cpu/broadwell/cpu.c b/arch/x86/cpu/broadwell/cpu.c index f30aebf..560b1f7 100644 --- a/arch/x86/cpu/broadwell/cpu.c +++ b/arch/x86/cpu/broadwell/cpu.c @@ -25,7 +25,7 @@ #include <asm/arch/pch.h> #include <asm/arch/rcb.h> -static int broadwell_init_cpu(void *ctx, struct event *event) +static int broadwell_init_cpu(void) { struct udevice *dev; int ret; @@ -40,7 +40,7 @@ static int broadwell_init_cpu(void *ctx, struct event *event) return 0; } -EVENT_SPY(EVT_DM_POST_INIT_F, broadwell_init_cpu); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, broadwell_init_cpu); void set_max_freq(void) { diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index c988d7f..e71a10b 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -54,7 +54,7 @@ int arch_cpu_init(void) return x86_cpu_init_f(); } -static int ivybridge_cpu_init(void *ctx, struct event *ev) +static int ivybridge_cpu_init(void) { struct pci_controller *hose; struct udevice *bus, *dev; @@ -86,7 +86,7 @@ static int ivybridge_cpu_init(void *ctx, struct event *ev) return 0; } -EVENT_SPY(EVT_DM_POST_INIT_F, ivybridge_cpu_init); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, ivybridge_cpu_init); #define PCH_EHCI0_TEMP_BAR0 0xe8000000 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 1be8e38..86d90d8 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -248,22 +248,16 @@ int arch_cpu_init(void) return 0; } -static int quark_init_pcie(void *ctx, struct event *event) -{ - /* - * Initialize PCIe controller - * - * Quark SoC holds the PCIe controller in reset following a power on. - * U-Boot needs to release the PCIe controller from reset. The PCIe - * controller (D23:F0/F1) will not be visible in PCI configuration - * space and any access to its PCI configuration registers will cause - * system hang while it is held in reset. - */ - quark_pcie_early_init(); - - return 0; -} -EVENT_SPY(EVT_DM_POST_INIT_F, quark_init_pcie); +/* + * Initialize PCIe controller + * + * Quark SoC holds the PCIe controller in reset following a power on. + * U-Boot needs to release the PCIe controller from reset. The PCIe + * controller (D23:F0/F1) will not be visible in PCI configuration + * space and any access to its PCI configuration registers will cause + * system hang while it is held in reset. + */ +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, quark_pcie_early_init); int checkcpu(void) { diff --git a/arch/x86/lib/fsp2/fsp_init.c b/arch/x86/lib/fsp2/fsp_init.c index afec7d0..aadc08c 100644 --- a/arch/x86/lib/fsp2/fsp_init.c +++ b/arch/x86/lib/fsp2/fsp_init.c @@ -19,7 +19,7 @@ #include <dm/uclass-internal.h> #include <asm/fsp2/fsp_internal.h> -int fsp_setup_pinctrl(void *ctx, struct event *event) +int fsp_setup_pinctrl(void) { struct udevice *dev; ofnode node; @@ -42,7 +42,7 @@ int fsp_setup_pinctrl(void *ctx, struct event *event) return ret; } -EVENT_SPY(EVT_DM_POST_INIT_F, fsp_setup_pinctrl); +EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, fsp_setup_pinctrl); #if !defined(CONFIG_TPL_BUILD) binman_sym_declare(ulong, intel_fsp_m, image_pos); |