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| author | Tom Rini <trini@konsulko.com> | 2024-04-10 20:01:42 -0600 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-04-10 20:01:42 -0600 |
| commit | a6915942419413153d09fbba28547318f1d77c55 (patch) | |
| tree | 0b91636c678154e795bddfebb5d4262d612b4dc4 /arch/x86 | |
| parent | 16303608f929a91021d9be91a090cff12a3d89df (diff) | |
| parent | eedbfc0c104f44a4f430bf106353f8b6b21a5f8a (diff) | |
| download | u-boot-a6915942419413153d09fbba28547318f1d77c55.zip u-boot-a6915942419413153d09fbba28547318f1d77c55.tar.gz u-boot-a6915942419413153d09fbba28547318f1d77c55.tar.bz2 | |
Merge patch series "Resolve issues with booting distros on x86"
Simon Glass <sjg@chromium.org> says:
This little series reprises the EFI-video fix, fixes a USB problem and
enables a boot script for coreboot.
It also moves to truetype fonts for coreboot and qemu-x86, since the
menus look much better and there are no strong size constraints.
With these changes it is possible to boot a Linux distro automatically
with U-Boot on x86, including when U-Boot is the second-stage
bootloader.
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/Kconfig | 8 | ||||
| -rw-r--r-- | arch/x86/config.mk | 4 | ||||
| -rw-r--r-- | arch/x86/cpu/x86_64/cpu.c | 12 | ||||
| -rw-r--r-- | arch/x86/dts/coreboot.dts | 10 |
4 files changed, 34 insertions, 0 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e5ee10a..23a1e21 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -723,6 +723,14 @@ config ROM_TABLE_SIZE hex default 0x10000 +config X86_HARDFP + bool "Support hardware floating point" + help + U-Boot generally does not make use of floating point. Where this is + needed, it can be enabled using this option. This adjusts the + start-up code for 64-bit mode and changes the compiler options for + 64-bit to enable SSE. + config HAVE_ITSS bool "Enable ITSS" help diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 26ec1af..2e3a711 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -27,9 +27,13 @@ ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 else PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -march=core2 -m64 + +ifndef CONFIG_X86_HARDFP PLATFORM_CPPFLAGS += -mno-mmx -mno-sse endif +endif # IS_32BIT + PLATFORM_RELFLAGS += -fdata-sections -ffunction-sections -fvisibility=hidden KBUILD_LDFLAGS += -Bsymbolic -Bsymbolic-functions diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c index 2647bff..5ea746e 100644 --- a/arch/x86/cpu/x86_64/cpu.c +++ b/arch/x86/cpu/x86_64/cpu.c @@ -10,6 +10,7 @@ #include <init.h> #include <asm/cpu.h> #include <asm/global_data.h> +#include <asm/processor-flags.h> DECLARE_GLOBAL_DATA_PTR; @@ -39,11 +40,22 @@ int x86_mp_init(void) return 0; } +/* enable SSE features for hardware floating point */ +static void setup_sse_features(void) +{ + asm ("mov %%cr4, %%rax\n" \ + "or %0, %%rax\n" \ + "mov %%rax, %%cr4\n" \ + : : "i" (X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT) : "eax"); +} + int x86_cpu_reinit_f(void) { /* set the vendor to Intel so that native_calibrate_tsc() works */ gd->arch.x86_vendor = X86_VENDOR_INTEL; gd->arch.has_mtrr = true; + if (IS_ENABLED(CONFIG_X86_HARDFP)) + setup_sse_features(); return 0; } diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts index dfce7c2..b867468 100644 --- a/arch/x86/dts/coreboot.dts +++ b/arch/x86/dts/coreboot.dts @@ -46,6 +46,16 @@ compatible = "coreboot-fb"; }; + bootstd { + compatible = "u-boot,boot-std"; + + theme { + font-size = <30>; + menu-inset = <3>; + menuitem-gap-y = <1>; + }; + }; + sysinfo { compatible = "coreboot,sysinfo"; }; |