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| author | Simon Glass <sjg@chromium.org> | 2023-05-04 16:54:55 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng@tinylab.org> | 2023-05-11 10:25:29 +0800 |
| commit | 7a187a89fd96e8f2344b47b7fd4d3a686da66f55 (patch) | |
| tree | f042fb8fa46cb123911767708c67fdf1e921d1ad /arch/x86 | |
| parent | 0fb19ffe3056e02408c4e14940d3635bbffd7295 (diff) | |
| download | u-boot-7a187a89fd96e8f2344b47b7fd4d3a686da66f55.zip u-boot-7a187a89fd96e8f2344b47b7fd4d3a686da66f55.tar.gz u-boot-7a187a89fd96e8f2344b47b7fd4d3a686da66f55.tar.bz2 | |
x86: Adjust search range for sysinfo table
Avoid searching starting at 0 since this memory may not be available,
e.g. if protection against NULL-pointer access is enabled. The table
cannot be there anyway, since the first 1KB of memory was originally
used for the interrupt table and coreboot avoids it.
Start at 0x400 instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/cpu/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 6fe6eaf..dddd281 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -351,8 +351,8 @@ long locate_coreboot_table(void) { long addr; - /* We look for LBIO in the first 4K of RAM and again at 960KB */ - addr = detect_coreboot_table_at(0x0, 0x1000); + /* We look for LBIO from addresses 1K-4K and again at 960KB */ + addr = detect_coreboot_table_at(0x400, 0xc00); if (addr < 0) addr = detect_coreboot_table_at(0xf0000, 0x1000); |