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| author | Simon Glass <sjg@chromium.org> | 2023-07-15 21:38:36 -0600 |
|---|---|---|
| committer | Bin Meng <bmeng@tinylab.org> | 2023-07-17 17:08:44 +0800 |
| commit | 4fb2536e5b17de99cfc44e985a1f617b1dfc0a22 (patch) | |
| tree | 454cf97dea9f484ba513be29130cad3c3912f30b /arch/x86/lib/spl.c | |
| parent | 3693d348958f2d6339adb20489dd31bc08ddde83 (diff) | |
| download | u-boot-4fb2536e5b17de99cfc44e985a1f617b1dfc0a22.zip u-boot-4fb2536e5b17de99cfc44e985a1f617b1dfc0a22.tar.gz u-boot-4fb2536e5b17de99cfc44e985a1f617b1dfc0a22.tar.bz2 | |
x86: Allow listing MTRRs in SPL
Move MTRR-listing code into a common file so it can be used from SPL.
Update the 'mtrr' command to call it.
Use this in SPL just before adjusting the MTRRs, so we can see the state
set up by the board. Only show it when debug is enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/lib/spl.c')
| -rw-r--r-- | arch/x86/lib/spl.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index ca1645f..b9d23e6 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -19,6 +19,7 @@ #include <asm/cpu_common.h> #include <asm/fsp2/fsp_api.h> #include <asm/global_data.h> +#include <asm/mp.h> #include <asm/mrccache.h> #include <asm/mtrr.h> #include <asm/pci.h> @@ -139,6 +140,12 @@ static int x86_spl_init(void) arch_setup_gd(gd->new_gd); gd->start_addr_sp = (ulong)ptr; + if (_LOG_DEBUG) { + ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP); + if (ret) + printf("mtrr_list failed\n"); + } + /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ ret = mtrr_add_request(MTRR_TYPE_WRBACK, (1ULL << 32) - CONFIG_XIP_ROM_SIZE, |