diff options
| author | Simon Glass <sjg@chromium.org> | 2020-11-04 09:57:15 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2020-11-05 14:58:45 +0800 |
| commit | 6571d873159789ee7caa571eafa5fa641005971c (patch) | |
| tree | bcb0f59b372597fae7916946cd6be44424a435bf /arch/x86/include/asm/msr-index.h | |
| parent | 1779b8a96a32706dc8e2e71187889b38d9822443 (diff) | |
| download | u-boot-6571d873159789ee7caa571eafa5fa641005971c.zip u-boot-6571d873159789ee7caa571eafa5fa641005971c.tar.gz u-boot-6571d873159789ee7caa571eafa5fa641005971c.tar.bz2 | |
x86: apl: Add core init for the SoC
Set up MSRs required for Apollo Lake. This enables Linux to use the
timers correctly. Also write the fixed MSRs for this platform.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 94e6b18..c49b422 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -68,7 +68,18 @@ #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce #define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2 -#define SINGLE_PCTL (1 << 11) +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK BIT(1) +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK BIT(10) +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK BIT(15) +#define SINGLE_PCTL BIT(11) + +/* ACPI PMIO Offset to C-state register */ +#define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 @@ -83,6 +94,10 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_VALUE 0x13 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) + #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 #define MSR_IA32_SYSENTER_EIP 0x00000176 @@ -453,6 +468,9 @@ #define MSR_AMD_PERF_CTL 0xc0010062 #define MSR_PMG_CST_CONFIG_CTL 0x000000e2 +/* CST Range (R/W) IO port block size */ +#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5 + #define MSR_PMG_IO_CAPTURE_ADR 0x000000e4 #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 |