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| author | Simon Glass <sjg@chromium.org> | 2019-08-24 07:22:49 -0600 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2019-10-15 08:40:02 -0600 |
| commit | 5e239183f62cc3740bf775e5204591cea5bf02ae (patch) | |
| tree | afd7ca413efa94db8b68b2f57d7c7d67fe7f0764 /arch/x86/dts | |
| parent | 2250ee6ee681564115d82f9f9c63497ccfb5fdd7 (diff) | |
| download | u-boot-5e239183f62cc3740bf775e5204591cea5bf02ae.zip u-boot-5e239183f62cc3740bf775e5204591cea5bf02ae.tar.gz u-boot-5e239183f62cc3740bf775e5204591cea5bf02ae.tar.bz2 | |
binman: x86: Separate out 16-bit reset and init code
At present these two sections of code are linked together into a single
2KB chunk in a single file. Some Intel SoCs like to have a FIT (Firmware
Interface Table) in the ROM and the pointer for this needs to go at
0xffffffc0 which is in the middle of these two sections.
Make use of the new 'reset' entry and change the existing 16-bit entry to
include just the 16-bit data.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/x86/dts')
| -rw-r--r-- | arch/x86/dts/u-boot.dtsi | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index daeb168..0e87b88 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -120,14 +120,23 @@ x86-start16-tpl { offset = <CONFIG_SYS_X86_START16>; }; + x86-reset16-tpl { + offset = <CONFIG_RESET_VEC_LOC>; + }; #elif defined(CONFIG_SPL) x86-start16-spl { offset = <CONFIG_SYS_X86_START16>; }; + x86-reset16-spl { + offset = <CONFIG_RESET_VEC_LOC>; + }; #else x86-start16 { offset = <CONFIG_SYS_X86_START16>; }; + x86-reset16 { + offset = <CONFIG_RESET_VEC_LOC>; + }; #endif }; #endif |