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| author | Sagar Shrikant Kadam <sagar.kadam@sifive.com> | 2019-07-09 05:23:44 -0700 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-08-15 13:42:28 +0800 |
| commit | 8836384c754295b1bbbb2910664c0d07de0dbde4 (patch) | |
| tree | b648be5a4a39ff52d4573120d385a4f439091a3c /arch/riscv | |
| parent | df33f8646855e65b8e7232c7fd5739e1ae1eb58b (diff) | |
| download | u-boot-8836384c754295b1bbbb2910664c0d07de0dbde4.zip u-boot-8836384c754295b1bbbb2910664c0d07de0dbde4.tar.gz u-boot-8836384c754295b1bbbb2910664c0d07de0dbde4.tar.bz2 | |
riscv : serial: use rx watermark to indicate rx data is present
In y-modem transfer mode, tstc/getc fail to check if there is any
data available / received in RX FIFO, and so y-modem transfer never
succeeds. Using receive watermark bit within ip register fixes the
issue.
This patch is based on commit c7392b7bc4e1 ("Use the RX watermark
interrupt pending bit for TSTC") available at[1]
[1] https://github.com/sifive/HiFive_U-Boot/tree/regression
Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>
Diffstat (limited to 'arch/riscv')
0 files changed, 0 insertions, 0 deletions