diff options
| author | Rick Chen <rick@andestech.com> | 2019-08-28 18:46:09 +0800 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2019-09-03 09:31:03 +0800 |
| commit | 7045ed9f1ad9bb2b8d19f3b5d39d7e1be8da36a6 (patch) | |
| tree | 0a7d13eefc015724d2bc1c482686ada4e54ee691 /arch/riscv | |
| parent | a8323d1816c978c012ea2fbbc844f0cbd5c82bdc (diff) | |
| download | u-boot-7045ed9f1ad9bb2b8d19f3b5d39d7e1be8da36a6.zip u-boot-7045ed9f1ad9bb2b8d19f3b5d39d7e1be8da36a6.tar.gz u-boot-7045ed9f1ad9bb2b8d19f3b5d39d7e1be8da36a6.tar.bz2 | |
riscv: cache: Flush L2 cache before jump to linux
Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/ax25/cache.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index cd95058..8f5455e 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -5,6 +5,9 @@ */ #include <common.h> +#include <dm.h> +#include <dm/uclass-internal.h> +#include <cache.h> void flush_dcache_all(void) { @@ -59,11 +62,18 @@ void dcache_enable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + asm volatile ( "csrr t1, mcache_ctl\n\t" "ori t0, t1, 0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_enable(dev); #endif #endif } @@ -72,12 +82,19 @@ void dcache_disable(void) { #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) #ifdef CONFIG_RISCV_NDS_CACHE + struct udevice *dev = NULL; + asm volatile ( "fence\n\t" "csrr t1, mcache_ctl\n\t" "andi t0, t1, ~0x2\n\t" "csrw mcache_ctl, t0\n\t" ); + + uclass_find_first_device(UCLASS_CACHE, &dev); + + if (dev) + cache_disable(dev); #endif #endif } |