aboutsummaryrefslogtreecommitdiff
path: root/arch/riscv
diff options
context:
space:
mode:
authorSimon Glass <sjg@chromium.org>2020-02-03 07:36:15 -0700
committerSimon Glass <sjg@chromium.org>2020-02-05 19:33:46 -0700
commit61b29b82683863a970fd4609a7c58512872616bc (patch)
tree5b83289e241abbef5906999bc26a13e0814585b5 /arch/riscv
parenta466db5adb58e486fbd8ae63536b03a70d69f68d (diff)
downloadu-boot-61b29b82683863a970fd4609a7c58512872616bc.zip
u-boot-61b29b82683863a970fd4609a7c58512872616bc.tar.gz
u-boot-61b29b82683863a970fd4609a7c58512872616bc.tar.bz2
dm: core: Require users of devres to include the header
At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/lib/andes_plic.c1
-rw-r--r--arch/riscv/lib/andes_plmt.c1
-rw-r--r--arch/riscv/lib/sifive_clint.c1
3 files changed, 3 insertions, 0 deletions
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 3868569..20529ab 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -17,6 +17,7 @@
#include <asm/io.h>
#include <asm/syscon.h>
#include <cpu.h>
+#include <linux/err.h>
/* pending register */
#define PENDING_REG(base, hart) ((ulong)(base) + 0x1000 + ((hart) / 4) * 4)
diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
index 84f4607..a7e90ca 100644
--- a/arch/riscv/lib/andes_plmt.c
+++ b/arch/riscv/lib/andes_plmt.c
@@ -13,6 +13,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/syscon.h>
+#include <linux/err.h>
/* mtime register */
#define MTIME_REG(base) ((ulong)(base))
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index d7899d1..5e0d257 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -13,6 +13,7 @@
#include <syscon.h>
#include <asm/io.h>
#include <asm/syscon.h>
+#include <linux/err.h>
/* MSIP registers */
#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)