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| author | Sean Anderson <seanga2@gmail.com> | 2020-01-27 16:39:44 -0500 |
|---|---|---|
| committer | Andes <uboot@andestech.com> | 2020-02-10 14:51:52 +0800 |
| commit | 404339759ef5e0bcd4fa7768d1148b1ace2d2bb6 (patch) | |
| tree | 66a614ed7e18e95440a779b3ad253db0f6504e83 /arch/riscv | |
| parent | 33a6259d72ba4d7a3e3f97e9cfadc34e6e4f52d3 (diff) | |
| download | u-boot-404339759ef5e0bcd4fa7768d1148b1ace2d2bb6.zip u-boot-404339759ef5e0bcd4fa7768d1148b1ace2d2bb6.tar.gz u-boot-404339759ef5e0bcd4fa7768d1148b1ace2d2bb6.tar.bz2 | |
riscv: Remove unnecessary instruction
The add instruction on risc-v can have any three sources and targets, so there
is no need for an intermediate mov.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/cpu/start.S | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index f3dccdb..6b3ff99 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -359,9 +359,8 @@ relocate_secondary_harts: call_board_init_r: jal invalidate_icache_all jal flush_dcache_all - la t0, board_init_r - mv t4, t0 /* offset of board_init_r() */ - add t4, t4, t6 /* real address of board_init_r() */ + la t0, board_init_r /* offset of board_init_r() */ + add t4, t0, t6 /* real address of board_init_r() */ /* * setup parameters for board_init_r */ |