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authorTom Rini <trini@konsulko.com>2023-10-02 10:55:44 -0400
committerTom Rini <trini@konsulko.com>2023-10-02 10:55:44 -0400
commitac897385bbfa30cfdfb62ccf24acfcd4b274b2ff (patch)
treeae567980737beb24ca24e2ee8cfeaf6eb9e26e3f /arch/riscv
parent4459ed60cb1e0562bc5b40405e2b4b9bbf766d57 (diff)
parente29b932aa07fa0226d325b35d96cd4eea0370129 (diff)
downloadu-boot-ac897385bbfa30cfdfb62ccf24acfcd4b274b2ff.zip
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Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/cpu/cpu.c14
-rw-r--r--arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi11
-rw-r--r--arch/riscv/include/asm/global_data.h3
-rw-r--r--arch/riscv/include/asm/system.h2
-rw-r--r--arch/riscv/lib/smp.c1
-rw-r--r--arch/riscv/lib/spl.c2
6 files changed, 22 insertions, 11 deletions
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 0b4208e..c1a9638 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -66,7 +66,7 @@ static inline bool supports_extension(char ext)
#endif /* CONFIG_CPU */
}
-static int riscv_cpu_probe(void *ctx, struct event *event)
+static int riscv_cpu_probe(void)
{
#ifdef CONFIG_CPU
int ret;
@@ -79,7 +79,7 @@ static int riscv_cpu_probe(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_R, riscv_cpu_probe);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_R, riscv_cpu_probe);
/*
* This is called on secondary harts just after the IPI is init'd. Currently
@@ -92,13 +92,9 @@ static void dummy_pending_ipi_clear(ulong hart, ulong arg0, ulong arg1)
}
#endif
-int riscv_cpu_setup(void *ctx, struct event *event)
+int riscv_cpu_setup(void)
{
- int ret;
-
- ret = riscv_cpu_probe(ctx, event);
- if (ret)
- return ret;
+ int __maybe_unused ret;
/* Enable FPU */
if (supports_extension('d') || supports_extension('f')) {
@@ -146,7 +142,7 @@ int riscv_cpu_setup(void *ctx, struct event *event)
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, riscv_cpu_setup);
int arch_early_init_r(void)
{
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 13f69da..5518531 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -103,4 +103,15 @@
};
};
};
+
+ spl-img {
+ filename = "spl/u-boot-spl.bin.normal.out";
+
+ mkimage {
+ args = "-T sfspl";
+
+ u-boot-spl {
+ };
+ };
+};
};
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 9d97517..937fa4d 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -32,6 +32,9 @@ struct arch_global_data {
ulong available_harts;
#endif
#endif
+#ifdef CONFIG_SMBIOS
+ ulong smbios_start; /* Start address of SMBIOS table */
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index ffa7649..87a804b 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -26,6 +26,6 @@ struct event;
} while (0)
/* Hook to set up the CPU (called from SPL too) */
-int riscv_cpu_setup(void *ctx, struct event *event);
+int riscv_cpu_setup(void);
#endif /* __ASM_RISCV_SYSTEM_H */
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 4f073a0..f3cd8b9 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -10,6 +10,7 @@
#include <asm/barrier.h>
#include <asm/global_data.h>
#include <asm/smp.h>
+#include <linux/printk.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c
index f4d3b67..9b242ed 100644
--- a/arch/riscv/lib/spl.c
+++ b/arch/riscv/lib/spl.c
@@ -28,7 +28,7 @@ __weak void board_init_f(ulong dummy)
if (ret)
panic("spl_early_init() failed: %d\n", ret);
- riscv_cpu_setup(NULL, NULL);
+ riscv_cpu_setup();
preloader_console_init();