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| author | Bin Meng <bmeng@tinylab.org> | 2023-06-21 23:11:45 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-12 13:21:40 +0800 |
| commit | 7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186 (patch) | |
| tree | 53e0539fb16d607724abcbc5b39a0e9cd4d1666d /arch/riscv/lib | |
| parent | 5764acb2617658af76c25285685e791ce6d0b051 (diff) | |
| download | u-boot-7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186.zip u-boot-7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186.tar.gz u-boot-7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186.tar.bz2 | |
riscv: clint: Update the sifive clint ipi driver to support aclint
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.
The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint ipi driver to
support ACLINT mswi device, by checking the per-driver data field of
the ACLINT mtimer driver to determine whether a syscon based approach
needs to be taken to get the base address of the ACLINT mswi device.
[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib')
| -rw-r--r-- | arch/riscv/lib/sifive_clint.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index ab22395..f242168 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -10,9 +10,12 @@ #include <common.h> #include <dm.h> +#include <regmap.h> +#include <syscon.h> #include <asm/global_data.h> #include <asm/io.h> #include <asm/smp.h> +#include <asm/syscon.h> #include <linux/err.h> /* MSIP registers */ @@ -30,7 +33,11 @@ int riscv_init_ipi(void) if (ret) return ret; - gd->arch.clint = dev_read_addr_ptr(dev); + if (dev_get_driver_data(dev) != 0) + gd->arch.clint = dev_read_addr_ptr(dev); + else + gd->arch.clint = syscon_get_first_range(RISCV_SYSCON_CLINT); + if (!gd->arch.clint) return -EINVAL; @@ -57,3 +64,15 @@ int riscv_get_ipi(int hart, int *pending) return 0; } + +static const struct udevice_id riscv_aclint_swi_ids[] = { + { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_CLINT }, + { } +}; + +U_BOOT_DRIVER(riscv_aclint_swi) = { + .name = "riscv_aclint_swi", + .id = UCLASS_SYSCON, + .of_match = riscv_aclint_swi_ids, + .flags = DM_FLAG_PRE_RELOC, +}; |