From 7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Wed, 21 Jun 2023 23:11:45 +0800 Subject: riscv: clint: Update the sifive clint ipi driver to support aclint This RISC-V ACLINT specification [1] defines a set of memory mapped devices which provide inter-processor interrupts (IPI) and timer functionalities for each HART on a multi-HART RISC-V platform. The RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, however the device tree binding is a new one. This change updates the sifive clint ipi driver to support ACLINT mswi device, by checking the per-driver data field of the ACLINT mtimer driver to determine whether a syscon based approach needs to be taken to get the base address of the ACLINT mswi device. [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc Signed-off-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/lib/sifive_clint.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'arch/riscv/lib') diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index ab22395..f242168 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -10,9 +10,12 @@ #include #include +#include +#include #include #include #include +#include #include /* MSIP registers */ @@ -30,7 +33,11 @@ int riscv_init_ipi(void) if (ret) return ret; - gd->arch.clint = dev_read_addr_ptr(dev); + if (dev_get_driver_data(dev) != 0) + gd->arch.clint = dev_read_addr_ptr(dev); + else + gd->arch.clint = syscon_get_first_range(RISCV_SYSCON_CLINT); + if (!gd->arch.clint) return -EINVAL; @@ -57,3 +64,15 @@ int riscv_get_ipi(int hart, int *pending) return 0; } + +static const struct udevice_id riscv_aclint_swi_ids[] = { + { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_CLINT }, + { } +}; + +U_BOOT_DRIVER(riscv_aclint_swi) = { + .name = "riscv_aclint_swi", + .id = UCLASS_SYSCON, + .of_match = riscv_aclint_swi_ids, + .flags = DM_FLAG_PRE_RELOC, +}; -- cgit v1.1