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author | Lukas Auer <lukas.auer@aisec.fraunhofer.de> | 2019-12-08 23:28:50 +0100 |
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committer | Andes <uboot@andestech.com> | 2019-12-10 08:23:10 +0800 |
commit | 8b3e97badf97d6e399014fb4a152031f8a0c94ba (patch) | |
tree | 63c6e428e63506f5c1010b905159c67b178332f0 /arch/riscv/lib/sifive_clint.c | |
parent | b86f6d1e649f237849297b5ec6b5566b7a92b2b4 (diff) | |
download | u-boot-8b3e97badf97d6e399014fb4a152031f8a0c94ba.zip u-boot-8b3e97badf97d6e399014fb4a152031f8a0c94ba.tar.gz u-boot-8b3e97badf97d6e399014fb4a152031f8a0c94ba.tar.bz2 |
riscv: add functions for reading the IPI status
Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'arch/riscv/lib/sifive_clint.c')
-rw-r--r-- | arch/riscv/lib/sifive_clint.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index d24e0d5..d7899d1 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -71,6 +71,15 @@ int riscv_clear_ipi(int hart) return 0; } +int riscv_get_ipi(int hart, int *pending) +{ + CLINT_BASE_GET(); + + *pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart)); + + return 0; +} + static const struct udevice_id sifive_clint_ids[] = { { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT }, { } |