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authormario.six@gdsys.cc <mario.six@gdsys.cc>2017-01-17 08:33:47 +0100
committerYork Sun <york.sun@nxp.com>2017-01-31 09:35:06 -0800
commite80311a5f09967b2c33a772c26983abfbc821140 (patch)
tree31f9b38ead0b52626eacc8e806db76c10686f16a /arch/powerpc
parentcf4128e53caa4f7b0a6586fc3f10690d5c05db31 (diff)
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powerpc: mpc83xx: Minimize r1 modification
The r1 register is modified several times during the cache-ram setup of the MPC83xx SoCs. Since this SP modification confuses debuggers, we use a general purpose register to compute the new stack pointer value, and only set the SP once after all computations are done. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Joakim Tjernlund <Joakim.Tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S13
1 files changed, 8 insertions, 5 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 0001687..c366f61 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -258,14 +258,17 @@ in_flash:
#endif
/* set up the stack pointer in our newly created
- * cache-ram (r1) */
- lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
- ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
+ * cache-ram; use r3 to keep the new SP for now to
+ * avoid overiding the SP it uselessly */
+ lis r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
+ ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
+ stwu r0, -4(r3) /* clear final stack frame so that */
+ stwu r0, -4(r3) /* stack backtraces terminate cleanly */
+ /* Finally, actually set SP */
+ mr r1, r3
/* let the C-code set up the rest */
/* */