diff options
| author | Tom Rini <trini@konsulko.com> | 2022-07-31 21:08:24 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-12 16:10:49 -0400 |
| commit | 8b549c0b23619afbc9b8d26379710ecb937e20e2 (patch) | |
| tree | d422e61b543b5f06d6fce3580acbc1a37f19a604 /arch/powerpc/include | |
| parent | 83505a7e9f8dd3e483d58f0519064bfac84e40a2 (diff) | |
| download | u-boot-8b549c0b23619afbc9b8d26379710ecb937e20e2.zip u-boot-8b549c0b23619afbc9b8d26379710ecb937e20e2.tar.gz u-boot-8b549c0b23619afbc9b8d26379710ecb937e20e2.tar.bz2 | |
Remove CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR et al
This removes the following symbols:
CONFIG_SYS_FSL_DSPI_BE
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR
CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET
CONFIG_SYS_FSL_DSP_DDR_ADDR
CONFIG_SYS_FSL_DSP_M2_RAM_ADDR
CONFIG_SYS_FSL_DSP_M3_RAM_ADDR
CONFIG_SYS_FSL_ERRATUM_A008751
CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
CONFIG_SYS_FSL_ESDHC_NUM
CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET
CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET
CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET
CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET
CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET
CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET
CONFIG_SYS_FSL_ISBC_VER
CONFIG_SYS_FSL_QSPI_LE
CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR
CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET
CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET
CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR
CONFIG_SYS_FSL_SRDS_NUM_PLLS
CONFIG_SYS_FSL_WDOG_BE
CONFIG_SYS_GP1DIR
CONFIG_SYS_GP1ODR
CONFIG_SYS_GP2DIR
CONFIG_SYS_GP2ODR
CONFIG_SYS_HALT_BEFOR_RAM_JUMP
CONFIG_SYS_HMI_BASE
FSL_QSPI_FLASH_NUM
FSL_QSPI_FLASH_SIZE
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 10 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 13 |
2 files changed, 0 insertions, 23 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 458c0a8..543b0c5 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -137,19 +137,12 @@ #elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 -#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 #elif defined(CONFIG_ARCH_BSC9132) #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 -#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 -#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 -#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 -#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #elif defined(CONFIG_ARCH_T4240) @@ -202,7 +195,6 @@ #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 -#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 @@ -212,7 +204,6 @@ #define CONFIG_SYS_FSL_SRIO_LIODN #else #define CONFIG_MAX_DSP_CPUS 2 -#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 @@ -288,7 +279,6 @@ #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY -#define CONFIG_SYS_FSL_ISBC_VER 2 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index b8bc584..7e88779 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1464,7 +1464,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080 -#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 @@ -1477,8 +1476,6 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 #define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 -#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 -#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 @@ -2576,20 +2573,10 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 -#if defined(CONFIG_ARCH_BSC9132) -#define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 -#define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ - (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) -#endif - #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_SCFG_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) -#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ - (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) -#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ - (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ |