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| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-03-02 16:26:26 +0100 |
|---|---|---|
| committer | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-04-06 14:50:03 +0200 |
| commit | 83945efacff3ee4ed15457b2b9b627aab9814eba (patch) | |
| tree | 103f493387c58920f5be740bcbbc00c6409bbe40 /arch/powerpc/include | |
| parent | e1fff66079d29ef59521771cf0aaa5ac4a834b50 (diff) | |
| download | u-boot-83945efacff3ee4ed15457b2b9b627aab9814eba.zip u-boot-83945efacff3ee4ed15457b2b9b627aab9814eba.tar.gz u-boot-83945efacff3ee4ed15457b2b9b627aab9814eba.tar.bz2 | |
spi: mpc8xxx: Add support for SPI on mpc832x
On mpc832x, SPI can be either handled by CPU or QE.
In order to work in CPU mode, bit 17 of SPMODE has to
be set to 1, that bit is called OP.
Also, data is located at a different place than the one expected
by the driver today. In 8 bits mode with REV set, data to be
transmitted is located in the most significant byte while
received data is located in second byte. So perform the
necessary shifts.
In order to differentiate with other CPUs, a new compatible is
added for mpc832x: fsl,mpc832x-spi
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/mpc8xxx_spi.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h index 83cfe23..8e9411a 100644 --- a/arch/powerpc/include/asm/mpc8xxx_spi.h +++ b/arch/powerpc/include/asm/mpc8xxx_spi.h @@ -12,6 +12,7 @@ #if defined(CONFIG_ARCH_MPC8308) || \ defined(CONFIG_ARCH_MPC8313) || \ + defined(CONFIG_ARCH_MPC832X) || \ defined(CONFIG_ARCH_MPC834X) || \ defined(CONFIG_ARCH_MPC837X) |