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author | Tom Rini <trini@konsulko.com> | 2022-11-16 13:10:41 -0500 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2022-12-05 16:06:08 -0500 |
commit | 65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8 (patch) | |
tree | e1b9902c5257875fc5fe8243e1e759594f90beed /arch/powerpc/include | |
parent | a322afc9f9b69dd52a9bc72937cd5adc18ea55c7 (diff) | |
download | u-boot-65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8.zip u-boot-65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8.tar.gz u-boot-65cc0e2a65d2c9f107b2f42db6396d9ade6c5ad8.tar.bz2 |
global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 42 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_lbc.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_liodn.h | 18 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_secure_boot.h | 20 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_83xx.h | 10 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 44 |
6 files changed, 68 insertions, 68 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 2edf0d6..d9e5a7d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -43,9 +43,9 @@ #elif defined(CONFIG_ARCH_P1023) #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 2 -#define CONFIG_SYS_QMAN_NUM_PORTALS 3 -#define CONFIG_SYS_BMAN_NUM_PORTALS 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 +#define CFG_SYS_QMAN_NUM_PORTALS 3 +#define CFG_SYS_BMAN_NUM_PORTALS 3 +#define CFG_SYS_FM_MURAM_SIZE 0x10000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) @@ -68,7 +68,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -78,7 +78,7 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CFG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -90,7 +90,7 @@ #define CFG_SYS_NUM_FM2_DTSEC 4 #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -103,7 +103,7 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM2_DTSEC 5 #define CFG_SYS_NUM_FM2_10GEC 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 #elif defined(CONFIG_ARCH_BSC9131) @@ -134,11 +134,11 @@ #define CFG_SYS_FSL_SRDS_3 #define CFG_SYS_FSL_SRDS_4 #define CFG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_PME_CLK 0 +#define CFG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 3 -#define CONFIG_SYS_FM2_CLK 3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM1_CLK 3 +#define CFG_SYS_FM2_CLK 3 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #define CFG_SYS_FSL_SRIO_MAX_PORTS 2 #define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -147,9 +147,9 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CFG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CFG_SYS_FM_MURAM_SIZE 0x60000 #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 @@ -173,11 +173,11 @@ #define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_PME_PLAT_CLK_DIV 2 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_FM_PLAT_CLK_DIV 1 -#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -191,9 +191,9 @@ #define CFG_SYS_NUM_FM1_10GEC 1 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_FM1_CLK 0 #define CONFIG_QBMAN_CLK_DIV 1 -#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CFG_SYS_FM_MURAM_SIZE 0x30000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 @@ -212,10 +212,10 @@ #define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif #define CONFIG_PME_PLAT_CLK_DIV 1 -#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV -#define CONFIG_SYS_FM1_CLK 0 +#define CFG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV +#define CFG_SYS_FM1_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CFG_SYS_FM_MURAM_SIZE 0x28000 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 5038cb9..a03f091 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -469,7 +469,7 @@ extern void print_lbc_regs(void); extern void init_early_memctl_regs(void); extern void upmconfig(uint upm, uint *table, uint size); -#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR) +#define LBC_BASE_ADDR ((fsl_lbc_t *)CFG_SYS_LBC_ADDR) #define get_lbc_lcrr() (in_be32(&(LBC_BASE_ADDR)->lcrr)) #define get_lbc_lbcr() (in_be32(&(LBC_BASE_ADDR)->lbcr)) #define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br)) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index de85bcf..0af3d89 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -18,15 +18,15 @@ struct srio_liodn_id_table { #define SET_SRIO_LIODN_1(port, idA) \ { .id = { idA }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_2(port, idA, idB) \ { .id = { idA, idB }, .num_ids = 2, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ - + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CFG_SYS_CCSRBAR, \ } #define SET_SRIO_LIODN_BASE(port, id_a) \ @@ -70,22 +70,22 @@ extern void fdt_fixup_liodn(void *blob); { .compat[0] = name1, \ .compat[1] = name2, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \ { .compat = name, \ .id = { idA }, .num_ids = 1, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \ { .compat = name, \ .id = { idA, idB }, .num_ids = 2, \ - .reg_offset = off + CONFIG_SYS_CCSRBAR, \ - .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \ + .reg_offset = off + CFG_SYS_CCSRBAR, \ + .compat_offset = compatoff + CFG_SYS_CCSRBAR_PHYS, \ } #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 3e70760..e8b2680 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -9,11 +9,11 @@ #ifdef CONFIG_NXP_ESBC #if defined(CONFIG_FSL_CORENET) -#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 +#define CFG_SYS_PBI_FLASH_BASE 0xc0000000 #else -#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000 +#define CFG_SYS_PBI_FLASH_BASE 0xce000000 #endif -#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000 +#define CFG_SYS_PBI_FLASH_WINDOW 0xcff80000 #if defined(CONFIG_TARGET_T2080QDS) || \ defined(CONFIG_TARGET_T2080RDB) || \ @@ -21,18 +21,18 @@ defined(CONFIG_TARGET_T1042D4RDB) || \ defined(CONFIG_TARGET_T1042RDB_PI) || \ defined(CONFIG_ARCH_T1024) -#undef CONFIG_SYS_INIT_L3_ADDR -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#undef CFG_SYS_INIT_L3_ADDR +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #if defined(CONFIG_RAMBOOT_PBL) -#undef CONFIG_SYS_INIT_L3_ADDR -#ifdef CONFIG_SYS_INIT_L3_VADDR -#define CONFIG_SYS_INIT_L3_ADDR \ - (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ +#undef CFG_SYS_INIT_L3_ADDR +#ifdef CFG_SYS_INIT_L3_VADDR +#define CFG_SYS_INIT_L3_ADDR \ + (CFG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ 0xbff00000 #else -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#define CFG_SYS_INIT_L3_ADDR 0xbff00000 #endif #endif diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 8e18202..19774f3 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -871,11 +871,11 @@ struct ccsr_gpio { #define CFG_SYS_MPC83xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET) -#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) +#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9ae6987..283fdf3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2445,10 +2445,10 @@ struct ccsr_pman { #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 /* In SFPv3, OSPR register is now at offset 0x200. * * So directly mapping sfp register map to this address */ -#define CONFIG_SYS_OSPR_OFFSET 0x200 -#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET) +#define CFG_SYS_OSPR_OFFSET 0x200 +#define CFG_SYS_SFP_OFFSET (0xE8000 + CFG_SYS_OSPR_OFFSET) #else -#define CONFIG_SYS_SFP_OFFSET 0xE8000 +#define CFG_SYS_SFP_OFFSET 0xE8000 #endif #define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 #define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 @@ -2489,7 +2489,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CFG_SYS_FSL_SEC_OFFSET 0x300000 #define CFG_SYS_FSL_JR0_OFFSET 0x301000 -#define CONFIG_SYS_SEC_MON_OFFSET 0x314000 +#define CFG_SYS_SEC_MON_OFFSET 0x314000 #define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000 #define CFG_SYS_FSL_QMAN_OFFSET 0x318000 #define CFG_SYS_FSL_BMAN_OFFSET 0x31a000 @@ -2542,13 +2542,13 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 #ifdef CONFIG_TSECV2 -#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#define CFG_SYS_TSEC1_OFFSET 0xB0000 #elif defined(CONFIG_TSECV2_1) -#define CONFIG_SYS_TSEC1_OFFSET 0x10000 +#define CFG_SYS_TSEC1_OFFSET 0x10000 #else -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CFG_SYS_TSEC1_OFFSET 0x24000 #endif -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 +#define CFG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) #define CFG_SYS_FSL_SEC_OFFSET 0x80000 @@ -2559,8 +2559,8 @@ struct ccsr_pman { #endif #define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 -#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 -#define CONFIG_SYS_SFP_OFFSET 0xE7000 +#define CFG_SYS_SEC_MON_OFFSET 0xE6000 +#define CFG_SYS_SFP_OFFSET 0xE7000 #define CFG_SYS_FSL_QMAN_OFFSET 0x88000 #define CFG_SYS_FSL_BMAN_OFFSET 0x8a000 #define CFG_SYS_FSL_FM1_OFFSET 0x100000 @@ -2574,9 +2574,9 @@ struct ccsr_pman { #define CFG_SYS_FSL_SRIO_OFFSET 0xC0000 #define CFG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) #define CFG_SYS_FSL_SCFG_ADDR \ - (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) + (CFG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) #define CFG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET) #define CFG_SYS_FSL_BMAN_ADDR \ @@ -2603,9 +2603,9 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) #define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) -#define CONFIG_SYS_LBC_ADDR \ +#define CFG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_IFC_ADDR \ +#define CFG_SYS_IFC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET) #define CFG_SYS_MPC85xx_ESPI_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET) @@ -2659,7 +2659,7 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET) #define CFG_SYS_FSL_SRIO_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET) -#define CONFIG_SYS_PAMU_ADDR \ +#define CFG_SYS_PAMU_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET) #define CFG_SYS_PCIE1_ADDR \ @@ -2667,14 +2667,14 @@ struct ccsr_pman { #define CFG_SYS_PCIE2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) -#define CONFIG_SYS_SFP_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) +#define CFG_SYS_SFP_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SFP_OFFSET) -#define CONFIG_SYS_SEC_MON_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET) +#define CFG_SYS_SEC_MON_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET) -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 struct ccsr_cluster_l2 { @@ -2735,7 +2735,7 @@ struct ccsr_cluster_l2 { (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ -#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 +#define CFG_SYS_DCSR_DCFG_OFFSET 0X20000 struct dcsr_dcfg_regs { u8 res_0[0x520]; u32 ecccr1; |