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| author | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2023-11-06 17:21:59 +0100 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2024-03-13 21:15:40 +0100 |
| commit | 6806a133cde6f99777925953ee046bf2f050d4ef (patch) | |
| tree | 94d43c8ebe4c4905f1050516ac38ac5f2e9d5577 /arch/mips | |
| parent | 811dd44b0b13cb1ea40392edfbe8ffa21c5b33ad (diff) | |
| download | u-boot-6806a133cde6f99777925953ee046bf2f050d4ef.zip u-boot-6806a133cde6f99777925953ee046bf2f050d4ef.tar.gz u-boot-6806a133cde6f99777925953ee046bf2f050d4ef.tar.bz2 | |
mips: fix change_k0_cca()
The intention of change_k0_cca() is to read the C0.Config register into
register $t0, update $t0 with the new cache coherency mode passed in $a0
and write back $t0 to C0.Config. With MIPS32 R2 or later instruction
sets, this can be achieved with a single instruction with INS. The
source and destination register of the INS instruction is passed as
first parameter. In case of change_k0_cca() it is register $t0. But
for writing back the updated value to C0.Config, the incorrect $a0
register is used. This is only correct in the MIPS32 R1 code path.
Fix the `mtc0` instruction to write back the value of the $t0 register.
Fix the MIPS32 R1 code path to also store the updated value in $t0.
Reported by user ddqxy138 on Github.
https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813cf4619
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/lib/cache_init.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 602741c..d64209d 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -431,9 +431,9 @@ LEAF(change_k0_cca) #else xor a0, a0, t0 andi a0, a0, CONF_CM_CMASK - xor a0, a0, t0 + xor t0, a0, t0 #endif - mtc0 a0, CP0_CONFIG + mtc0 t0, CP0_CONFIG jr.hb ra END(change_k0_cca) |