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| author | Horatiu Vultur <horatiu.vultur@microchip.com> | 2019-04-15 11:56:36 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2019-05-03 16:42:23 +0200 |
| commit | 72e224b864baa4905b9c5997223baa3e65725be7 (patch) | |
| tree | 9954c6087815c7699351f802e8cfcd01330c69d3 /arch/mips/mach-mscc/reset.c | |
| parent | b4ee6daad7a2604ca9466b2ba48de86cc27d381f (diff) | |
| download | u-boot-72e224b864baa4905b9c5997223baa3e65725be7.zip u-boot-72e224b864baa4905b9c5997223baa3e65725be7.tar.gz u-boot-72e224b864baa4905b9c5997223baa3e65725be7.tar.bz2 | |
mips: mscc: serval: Fix reset
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Diffstat (limited to 'arch/mips/mach-mscc/reset.c')
| -rw-r--r-- | arch/mips/mach-mscc/reset.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/mach-mscc/reset.c b/arch/mips/mach-mscc/reset.c index a555fc9..a121457 100644 --- a/arch/mips/mach-mscc/reset.c +++ b/arch/mips/mach-mscc/reset.c @@ -36,7 +36,7 @@ void _machine_restart(void) /* Do global reset */ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST); - for (i = 0; i < 1000; i++) + for (i = 0; i < 2000; i++) ; /* Power down DDR for clean DDR re-training */ |