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| author | Álvaro Fernández Rojas <noltari@gmail.com> | 2017-04-25 00:39:20 +0200 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2017-05-10 16:16:09 +0200 |
| commit | ee422142f454d54f0ed39a2cbf083ff12e98a3e1 (patch) | |
| tree | ba1a8bc79898349405ecd9955001be20548a4d1d /arch/mips/cpu | |
| parent | 193030e5916960f101e1ba406510980452bc47b6 (diff) | |
| download | u-boot-ee422142f454d54f0ed39a2cbf083ff12e98a3e1.zip u-boot-ee422142f454d54f0ed39a2cbf083ff12e98a3e1.tar.gz u-boot-ee422142f454d54f0ed39a2cbf083ff12e98a3e1.tar.bz2 | |
MIPS: add initial infrastructure for Broadcom MIPS SoCs
CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/mips/cpu')
| -rw-r--r-- | arch/mips/cpu/start.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index a6b7a04..d01ee9f 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -151,8 +151,13 @@ reset: mfc0 t0, CP0_GLOBALNUMBER #endif +#ifdef CONFIG_ARCH_BMIPS +1: mfc0 t0, CP0_DIAGNOSTIC, 3 + and t0, t0, (1 << 31) +#else 1: mfc0 t0, CP0_EBASE and t0, t0, EBASE_CPUNUM +#endif /* Hang if this isn't the first CPU in the system */ 2: beqz t0, 4f |