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| author | Ovidiu Panait <ovpanait@gmail.com> | 2022-05-31 21:14:29 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-06-24 14:16:00 +0200 |
| commit | 84488fc69348367ee693ea4ab6affe3cbcae97a0 (patch) | |
| tree | 54e6bf04e2b63e2ac66d64d38a80b14d4c08d427 /arch/microblaze | |
| parent | 73b8ee62a0a0aa03b789e5299a00cf8e6adf23ac (diff) | |
| download | u-boot-84488fc69348367ee693ea4ab6affe3cbcae97a0.zip u-boot-84488fc69348367ee693ea4ab6affe3cbcae97a0.tar.gz u-boot-84488fc69348367ee693ea4ab6affe3cbcae97a0.tar.bz2 | |
microblaze: cache: introduce Kconfig options for icache/dcache sizes
Replace XILINX_DCACHE_BYTE_SIZE macro with two Kconfig symbols for
instruction and data caches sizes, respectively:
CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE
CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE
Also, get rid of the hardcoded value in icache_disable().
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220531181435.3473549-8-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com> (s/bralid/brlid/g)
Diffstat (limited to 'arch/microblaze')
| -rw-r--r-- | arch/microblaze/cpu/cache.c | 5 | ||||
| -rw-r--r-- | arch/microblaze/cpu/start.S | 4 | ||||
| -rw-r--r-- | arch/microblaze/lib/bootm.c | 2 |
3 files changed, 5 insertions, 6 deletions
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index e362a34..d5c0afd 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -65,8 +65,7 @@ void icache_enable(void) void icache_disable(void) { - /* we are not generate ICACHE size -> flush whole cache */ - __invalidate_icache(0, 32768); + __invalidate_icache(0, CONFIG_XILINX_MICROBLAZE0_ICACHE_SIZE); MSRCLR(0x20); } @@ -78,7 +77,7 @@ void dcache_enable(void) void dcache_disable(void) { - __flush_dcache(0, XILINX_DCACHE_BYTE_SIZE); + __flush_dcache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); MSRCLR(0x80); } diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index cd47b0f..6e3ffaf 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -99,7 +99,7 @@ uboot_sym_start: /* Flush cache before enable cache */ addik r5, r0, 0 - addik r6, r0, XILINX_DCACHE_BYTE_SIZE + addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE brlid r15, flush_cache nop @@ -350,7 +350,7 @@ relocate_code: /* Flush caches to ensure consistency */ addik r5, r0, 0 - addik r6, r0, XILINX_DCACHE_BYTE_SIZE + addik r6, r0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE brlid r15, flush_cache nop diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index dba6226..48e0533 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -57,7 +57,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) "(fake run for tracing)" : ""); bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); - flush_cache(0, XILINX_DCACHE_BYTE_SIZE); + flush_cache(0, CONFIG_XILINX_MICROBLAZE0_DCACHE_SIZE); if (!fake) { /* |