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| author | Ye Li <ye.li@nxp.com> | 2023-04-28 12:08:39 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2023-05-21 16:54:41 +0200 |
| commit | 662f05fcb6798277c69700c7deadd1c3c6a1b363 (patch) | |
| tree | 0874722b9915077f1ce29d318388137759c47cbc /arch/arm | |
| parent | 4699ffb202615a15376e60f2a7482a322c5bc6ec (diff) | |
| download | u-boot-662f05fcb6798277c69700c7deadd1c3c6a1b363.zip u-boot-662f05fcb6798277c69700c7deadd1c3c6a1b363.tar.gz u-boot-662f05fcb6798277c69700c7deadd1c3c6a1b363.tar.bz2 | |
ddr: imx9: Add workaround for DDRPHY rank-to-rank errata
According to DDRPHY errata, the Rank-to-Rank Spacing and tphy_rdcsgap
specification does not include the Critical Delay Difference (CDD) to
properly define the required rank-to-rank read command spacing after
executing PHY training firmware.
Following the errata workaround, at the end of data training, we get
all CDD values through the MessageBlock, then re-configure the DDRC
timing of WWT/WRT/RRT/RWT with comparing MAX CDD values.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-imx9/ddr.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx9/ddr.h b/arch/arm/include/asm/arch-imx9/ddr.h index 62e6f7d..8e4f946 100644 --- a/arch/arm/include/asm/arch-imx9/ddr.h +++ b/arch/arm/include/asm/arch-imx9/ddr.h @@ -14,7 +14,9 @@ #define DDRMIX_BLK_CTRL_BASE 0x4E010000 #define REG_DDRDSR_2 (DDR_CTL_BASE + 0xB24) +#define REG_DDR_TIMING_CFG_0 (DDR_CTL_BASE + 0x104) #define REG_DDR_SDRAM_CFG (DDR_CTL_BASE + 0x110) +#define REG_DDR_TIMING_CFG_4 (DDR_CTL_BASE + 0x160) #define REG_DDR_DEBUG_19 (DDR_CTL_BASE + 0xF48) #define SRC_BASE_ADDR (0x44460000) |