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| author | Eddie James <eajames@linux.ibm.com> | 2019-08-15 14:29:37 -0500 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2019-09-05 15:27:31 +0800 |
| commit | 38c9f08b41ed9e6625b56320b78d4954cbf5fae6 (patch) | |
| tree | d9b9afa43dbfe8ccb85466f4456864f3243bbfed /arch/arm | |
| parent | 6cf8a903c5e6723104b07b0fddc4a703556e558a (diff) | |
| download | u-boot-38c9f08b41ed9e6625b56320b78d4954cbf5fae6.zip u-boot-38c9f08b41ed9e6625b56320b78d4954cbf5fae6.tar.gz u-boot-38c9f08b41ed9e6625b56320b78d4954cbf5fae6.tar.bz2 | |
clk: aspeed: Add support for SD clock
Add code to enable the SD clock on the ast2500 SoC.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h index 4988ced..8db4901 100644 --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h @@ -22,6 +22,8 @@ #define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT) #define SCU_PCLK_DIV_SHIFT 23 #define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT) +#define SCU_SDCLK_DIV_SHIFT 12 +#define SCU_SDCLK_DIV_MASK (7 << SCU_SDCLK_DIV_SHIFT) #define SCU_HPLL_DENUM_SHIFT 0 #define SCU_HPLL_DENUM_MASK 0x1f #define SCU_HPLL_NUM_SHIFT 5 @@ -107,6 +109,7 @@ #define SCU_CLKSTOP_MAC1 (1 << 20) #define SCU_CLKSTOP_MAC2 (1 << 21) +#define SCU_CLKSTOP_SDCLK (1 << 27) #define SCU_D2PLL_EXT1_OFF (1 << 0) #define SCU_D2PLL_EXT1_BYPASS (1 << 1) |