Merge branch '2023-08-18-assorted-updates' into next

- Use built-in ffs/fls on ARM, fix a PIE issue in SPL on ARMv8, bcm283x
  and mediatek updates, whitespace fix in UFS uclass, make CI use
  "tools-only" defconfig for more tests, add TI TCA9554 GPIO support,
  cache alignment fix for SCSI, and fix a problem with
  SYS_MMCSD_RAW_MODE_ARGS_SECTOR in SPL.

7 files changed, 147 insertions, 4 deletions

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index f3ea858..6cc1d26 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -58,7 +58,7 @@ reset:
 .globl	save_boot_params_ret
 save_boot_params_ret:
 
-#if CONFIG_POSITION_INDEPENDENT
+#if CONFIG_POSITION_INDEPENDENT && !defined(CONFIG_SPL_BUILD)
 	/* Verify that we're 4K aligned.  */
 	adr	x0, _start
 	ands	x0, x0, #0xfff
diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
index 1525630..c156a81 100644
--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
@@ -76,12 +76,12 @@
 &eth {
 	status = "okay";
 	mediatek,gmac-id = <0>;
-	phy-mode = "sgmii";
+	phy-mode = "2500base-x";
 	mediatek,switch = "mt7531";
 	reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
 
 	fixed-link {
-		speed = <1000>;
+		speed = <2500>;
 		full-duplex;
 	};
 };
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index ddd629e..ac476d5 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/mt7988-clk.h>
 #include <dt-bindings/reset/mt7988-reset.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	compatible = "mediatek,mt7988-rfb";
@@ -161,6 +162,65 @@
 		#clock-cells = <1>;
 	};
 
+	dummy_clk: dummy12m {
+		compatible = "fixed-clock";
+		clock-frequency = <12000000>;
+		#clock-cells = <0>;
+		/* must need this line, or uart uanable to get dummy_clk */
+		bootph-all;
+	};
+
+	xhci1: xhci@11200000 {
+		compatible = "mediatek,mt7988-xhci",
+			     "mediatek,mtk-xhci";
+		reg = <0 0x11200000 0 0x2e00>,
+		      <0 0x11203e00 0 0x0100>;
+		reg-names = "mac", "ippc";
+		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+		phys = <&tphyu2port0 PHY_TYPE_USB2>,
+		       <&tphyu3port0 PHY_TYPE_USB3>;
+		clocks = <&dummy_clk>,
+			 <&dummy_clk>,
+			 <&dummy_clk>,
+			 <&dummy_clk>,
+			 <&dummy_clk>;
+		clock-names = "sys_ck",
+			      "xhci_ck",
+			      "ref_ck",
+			      "mcu_ck",
+			      "dma_ck";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		status = "okay";
+	};
+
+	usbtphy: usb-phy@11c50000 {
+		compatible = "mediatek,mt7988",
+			     "mediatek,generic-tphy-v2";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "okay";
+
+		tphyu2port0: usb-phy@11c50000 {
+			reg = <0 0x11c50000 0 0x700>;
+			clocks = <&dummy_clk>;
+			clock-names = "ref";
+			#phy-cells = <1>;
+			status = "okay";
+		};
+
+		tphyu3port0: usb-phy@11c50700 {
+			reg = <0 0x11c50700 0 0x900>;
+			clocks = <&dummy_clk>;
+			clock-names = "ref";
+			#phy-cells = <1>;
+			mediatek,usb3-pll-ssc-delta;
+			mediatek,usb3-pll-ssc-delta1;
+			status = "okay";
+		};
+	};
+
 	xfi_pextp0: syscon@11f20000 {
 		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
 		reg = <0 0x11f20000 0 0x10000>;
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index fa85486..8e89783 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -15,9 +15,34 @@
 #ifndef __ASM_ARM_BITOPS_H
 #define __ASM_ARM_BITOPS_H
 
+#if __LINUX_ARM_ARCH__ < 5
+
 #include <asm-generic/bitops/__ffs.h>
 #include <asm-generic/bitops/__fls.h>
 #include <asm-generic/bitops/fls.h>
+
+#else
+
+#define PLATFORM_FFS
+#define PLATFORM_FLS
+
+#if !IS_ENABLED(CONFIG_HAS_THUMB2) && CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
+
+unsigned long __fls(unsigned long word);
+unsigned long __ffs(unsigned long word);
+int fls(unsigned int x);
+int ffs(int x);
+
+#else
+
+#include <asm-generic/bitops/builtin-__fls.h>
+#include <asm-generic/bitops/builtin-__ffs.h>
+#include <asm-generic/bitops/builtin-fls.h>
+#include <asm-generic/bitops/builtin-ffs.h>
+
+#endif
+#endif
+
 #include <asm-generic/bitops/fls64.h>
 
 #ifdef __KERNEL__
@@ -113,7 +138,7 @@ static inline int test_bit(int nr, const void * addr)
 
 static inline int __ilog2(unsigned int x)
 {
-	return generic_fls(x) - 1;
+	return fls(x) - 1;
 }
 
 #define ffz(x)  __ffs(~(x))
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 62cf80f..b1bcd37 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -113,6 +113,11 @@ AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
 AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
 AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
 AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
+
+# This is only necessary to force ARM mode on THUMB1 targets.
+ifneq ($(CONFIG_SYS_ARM_ARCH),4)
+obj-y   += bitops.o
+endif
 endif
 endif
 
diff --git a/arch/arm/lib/bitops.S b/arch/arm/lib/bitops.S
new file mode 100644
index 0000000..29d1524
--- /dev/null
+++ b/arch/arm/lib/bitops.S
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2023 Sean Anderson <sean.anderson@seco.com>
+ *
+ * ARM bitops to call when using THUMB1, which doesn't have these instructions.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+.pushsection .text.__fls
+ENTRY(__fls)
+	clz	r0, r0
+	rsb	r0, r0, #31
+	ret	lr
+ENDPROC(__fls)
+.popsection
+
+.pushsection .text.__ffs
+ENTRY(__ffs)
+	rsb	r3, r0, #0
+	and	r0, r0, r3
+	clz	r0, r0
+	rsb	r0, r0, #31
+	ret	lr
+ENDPROC(__ffs)
+.popsection
+
+.pushsection .text.fls
+ENTRY(fls)
+	cmp	r0, #0
+	clzne	r0, r0
+	rsbne	r0, r0, #32
+	ret	lr
+ENDPROC(fls)
+.popsection
+
+.pushsection .text.ffs
+ENTRY(ffs)
+	rsb	r3, r0, #0
+	and	r0, r0, r3
+	clz	r0, r0
+	rsb	r0, r0, #32
+	ret	lr
+ENDPROC(ffs)
+.popsection
diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c
index 183650a..7265faf 100644
--- a/arch/arm/mach-bcm283x/init.c
+++ b/arch/arm/mach-bcm283x/init.c
@@ -146,6 +146,14 @@ int mach_cpu_init(void)
 	return 0;
 }
 
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	printf("CPU: BCM283x\n");
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_ARMV7_LPAE
 #ifdef CONFIG_TARGET_RPI_4_32B
 #define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT	0xffc00000UL