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| author | Tom Rini <trini@konsulko.com> | 2020-05-04 09:29:42 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-04 09:29:42 -0400 |
| commit | 143414c03fa72468fa8ce0d1ded21a4a616400f9 (patch) | |
| tree | 823d7657534ae619e6e937e2f7d303e64885fbab /arch/arm | |
| parent | 8510580f2e85a8687b40fe5fc3d8c060e5278505 (diff) | |
| parent | ea0f768e2c835d2b77bdc1db7d4ab1416e45e432 (diff) | |
| download | u-boot-143414c03fa72468fa8ce0d1ded21a4a616400f9.zip u-boot-143414c03fa72468fa8ce0d1ded21a4a616400f9.tar.gz u-boot-143414c03fa72468fa8ce0d1ded21a4a616400f9.tar.bz2 | |
Merge tag 'u-boot-imx-20200502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX for 2020.07
----------------
- imxrt: fix LCD clock, fix doc
- new board: Coral Dev
- imx8: enable Cache in SPL. SNVS, update SCFW API
- imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
- MX6ULL : is_imx6ull to include i.MX6ULZ
- Net: add config to enable TXC delay
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
Diffstat (limited to 'arch/arm')
30 files changed, 2613 insertions, 168 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c57a646..559d3ab 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -736,6 +736,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-verdin.dtb \ imx8mn-ddr4-evk.dtb \ imx8mq-evk.dtb \ + imx8mq-phanbell.dtb \ imx8mp-evk.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index 3502602..b5c1210 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -3,6 +3,14 @@ * Copyright 2019 NXP */ +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + &{/soc@0} { u-boot,dm-pre-reloc; u-boot,dm-spl; @@ -117,3 +125,7 @@ &fec1 { phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi index e60b9fa..fe6bb9b 100644 --- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi @@ -3,6 +3,14 @@ * Copyright 2020 Toradex */ +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + &aips1 { u-boot,dm-spl; u-boot,dm-pre-reloc; @@ -105,3 +113,7 @@ &usdhc3 { u-boot,dm-spl; }; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index 8aafad2..1e5e115 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -12,7 +12,6 @@ #include "imx8mm-pinfunc.h" / { - compatible = "fsl,imx8mm"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -141,11 +140,6 @@ }; }; - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; - }; - osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -233,7 +227,7 @@ ranges = <0x0 0x0 0x0 0x3e000000>; aips1: bus@30000000 { - compatible = "fsl,aips-bus", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x30000000 0x30000000 0x400000>; @@ -394,7 +388,7 @@ }; sdma2: dma-controller@302c0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; reg = <0x302c0000 0x10000>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>, @@ -405,7 +399,7 @@ }; sdma3: dma-controller@302b0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; reg = <0x302b0000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>, @@ -439,7 +433,7 @@ }; anatop: anatop@30360000 { - compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus"; + compatible = "fsl,imx8mm-anatop", "syscon"; reg = <0x30360000 0x10000>; }; @@ -479,14 +473,18 @@ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, - <&clk IMX8MM_VIDEO_PLL1>; + <&clk IMX8MM_VIDEO_PLL1>, + <&clk IMX8MM_AUDIO_PLL1>, + <&clk IMX8MM_AUDIO_PLL2>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, <&clk IMX8MM_SYS_PLL1_800M>; assigned-clock-rates = <0>, <400000000>, <400000000>, <750000000>, - <594000000>; + <594000000>, + <393216000>, + <361267200>; }; src: reset-controller@30390000 { @@ -498,7 +496,7 @@ }; aips2: bus@30400000 { - compatible = "fsl,aips-bus", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x30400000 0x30400000 0x400000>; @@ -557,7 +555,7 @@ }; aips3: bus@30800000 { - compatible = "fsl,aips-bus", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x30800000 0x30800000 0x400000>; @@ -638,6 +636,36 @@ status = "disabled"; }; + crypto: crypto@30900000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_AHB>, + <&clk IMX8MM_CLK_IPG_ROOT>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + i2c1: i2c@30a20000 { compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c"; #address-cells = <1>; @@ -698,8 +726,6 @@ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; - assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -728,8 +754,6 @@ <&clk IMX8MM_CLK_NAND_USDHC_BUS>, <&clk IMX8MM_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; - assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; - assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -737,11 +761,11 @@ }; sdma1: dma-controller@30bd0000 { - compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma"; + compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>, - <&clk IMX8MM_CLK_SDMA1_ROOT>; + <&clk IMX8MM_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; @@ -776,7 +800,7 @@ }; aips4: bus@32c00000 { - compatible = "fsl,aips-bus", "simple-bus"; + compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; @@ -859,6 +883,16 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + }; + ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 8d61597..4419679 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -3,6 +3,14 @@ * Copyright 2019 NXP */ +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + &{/soc@0} { u-boot,dm-pre-reloc; u-boot,dm-spl; @@ -90,3 +98,7 @@ &usdhc3 { u-boot,dm-spl; }; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 4675ada..24a93ac 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -3,6 +3,14 @@ * Copyright 2019 NXP */ +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; +}; + &{/soc@0} { u-boot,dm-pre-reloc; u-boot,dm-spl; @@ -119,3 +127,7 @@ &usdhc3 { u-boot,dm-spl; }; + +&wdog1 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mq-phanbell.dts b/arch/arm/dts/imx8mq-phanbell.dts new file mode 100644 index 0000000..4892ad5 --- /dev/null +++ b/arch/arm/dts/imx8mq-phanbell.dts @@ -0,0 +1,417 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "Google i.MX8MQ Phanbell"; + compatible = "google,imx8mq-phanbell", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x00000000 0x40000000 0 0x40000000>; + }; + + pmic_osc: clock-pmic { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "pmic_osc"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71837"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + #clock-cells = <0>; + clocks = <&pmic_osc>; + clock-output-names = "pmic_clk"; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <900000>; + rohm,dvs-idle-voltage = <900000>; + rohm,dvs-suspend-voltage = <800000>; + }; + + buck2: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3: BUCK3 { + regulator-name = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + rohm,dvs-run-voltage = <900000>; + }; + + buck4: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + rohm,dvs-run-voltage = <900000>; + }; + + buck5: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7: BUCK7 { + regulator-name = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8: BUCK8 { + regulator-name = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7: LDO7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <50>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 5ade636..b525654 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -26,6 +26,8 @@ #define MXC_CPU_MX7S 0x71 /* dummy ID */ #define MXC_CPU_MX7D 0x72 #define MXC_CPU_IMX8MQ 0x82 +#define MXC_CPU_IMX8MD 0x83 /* dummy ID */ +#define MXC_CPU_IMX8MQL 0x84 /* dummy ID */ #define MXC_CPU_IMX8MM 0x85 /* dummy ID */ #define MXC_CPU_IMX8MML 0x86 /* dummy ID */ #define MXC_CPU_IMX8MMD 0x87 /* dummy ID */ @@ -33,6 +35,11 @@ #define MXC_CPU_IMX8MMS 0x89 /* dummy ID */ #define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */ #define MXC_CPU_IMX8MN 0x8b /* dummy ID */ +#define MXC_CPU_IMX8MND 0x8c /* dummy ID */ +#define MXC_CPU_IMX8MNS 0x8d /* dummy ID */ +#define MXC_CPU_IMX8MNL 0x8e /* dummy ID */ +#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ +#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ #define MXC_CPU_IMX8MP 0x182/* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 8e1e9bb..c1a9c35 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -8,6 +8,11 @@ #define SC_RPC_H /* Note: Check SCFW API Released DOC before you want to modify something */ +/* Defines */ + +#define SCFW_API_VERSION_MAJOR 1U +#define SCFW_API_VERSION_MINOR 15U + #define SC_RPC_VERSION 1U #define SC_RPC_MAX_MSG 8U @@ -17,9 +22,13 @@ #define RPC_SVC(MSG) ((MSG)->svc) #define RPC_FUNC(MSG) ((MSG)->func) #define RPC_R8(MSG) ((MSG)->func) +#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ + (s64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) #define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) #define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) +#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ + (u64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) #define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) #define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) @@ -76,6 +85,8 @@ struct sc_rpc_msg_s { #define PM_FUNC_REBOOT 9U #define PM_FUNC_REBOOT_PARTITION 12U #define PM_FUNC_CPU_START 11U +#define PM_FUNC_CPU_RESET 23U +#define PM_FUNC_RESOURCE_RESET 29U #define PM_FUNC_IS_PARTITION_STARTED 24U /* MISC RPC */ @@ -160,26 +171,59 @@ struct sc_rpc_msg_s { #define RM_FUNC_DUMP 27U /* SECO RPC */ -#define SECO_FUNC_UNKNOWN 0 -#define SECO_FUNC_IMAGE_LOAD 1U -#define SECO_FUNC_AUTHENTICATE 2U -#define SECO_FUNC_FORWARD_LIFECYCLE 3U -#define SECO_FUNC_RETURN_LIFECYCLE 4U -#define SECO_FUNC_COMMIT 5U -#define SECO_FUNC_ATTEST_MODE 6U -#define SECO_FUNC_ATTEST 7U -#define SECO_FUNC_GET_ATTEST_PKEY 8U -#define SECO_FUNC_GET_ATTEST_SIGN 9U -#define SECO_FUNC_ATTEST_VERIFY 10U -#define SECO_FUNC_GEN_KEY_BLOB 11U -#define SECO_FUNC_LOAD_KEY 12U -#define SECO_FUNC_GET_MP_KEY 13U -#define SECO_FUNC_UPDATE_MPMR 14U -#define SECO_FUNC_GET_MP_SIGN 15U -#define SECO_FUNC_BUILD_INFO 16U -#define SECO_FUNC_CHIP_INFO 17U -#define SECO_FUNC_ENABLE_DEBUG 18U -#define SECO_FUNC_GET_EVENT 19U -#define SECO_FUNC_FUSE_WRITE 20U +#define SECO_FUNC_UNKNOWN 0 /* Unknown function */ +#define SECO_FUNC_IMAGE_LOAD 1U /* Index for seco_image_load() RPC call */ +#define SECO_FUNC_AUTHENTICATE 2U /* Index for seco_authenticate() RPC call */ +#define SECO_FUNC_ENH_AUTHENTICATE 24U /* Index for sc_seco_enh_authenticate() RPC call */ +#define SECO_FUNC_FORWARD_LIFECYCLE 3U /* Index for seco_forward_lifecycle() RPC call */ +#define SECO_FUNC_RETURN_LIFECYCLE 4U /* Index for seco_return_lifecycle() RPC call */ +#define SECO_FUNC_COMMIT 5U /* Index for seco_commit() RPC call */ +#define SECO_FUNC_ATTEST_MODE 6U /* Index for seco_attest_mode() RPC call */ +#define SECO_FUNC_ATTEST 7U /* Index for seco_attest() RPC call */ +#define SECO_FUNC_GET_ATTEST_PKEY 8U /* Index for seco_get_attest_pkey() RPC call */ +#define SECO_FUNC_GET_ATTEST_SIGN 9U /* Index for seco_get_attest_sign() RPC call */ +#define SECO_FUNC_ATTEST_VERIFY 10U /* Index for seco_attest_verify() RPC call */ +#define SECO_FUNC_GEN_KEY_BLOB 11U /* Index for seco_gen_key_blob() RPC call */ +#define SECO_FUNC_LOAD_KEY 12U /* Index for seco_load_key() RPC call */ +#define SECO_FUNC_GET_MP_KEY 13U /* Index for seco_get_mp_key() RPC call */ +#define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */ +#define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */ +#define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */ +#define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */ +#define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */ +#define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */ +#define SECO_FUNC_FUSE_WRITE 20U /* Index for seco_fuse_write() RPC call */ +#define SECO_FUNC_PATCH 21U /* Index for sc_seco_patch() RPC call */ +#define SECO_FUNC_START_RNG 22U /* Index for sc_seco_start_rng() RPC call */ +#define SECO_FUNC_SAB_MSG 23U /* Index for sc_seco_sab_msg() RPC call */ +#define SECO_FUNC_SECVIO_ENABLE 25U /* Index for sc_seco_secvio_enable() RPC call */ +#define SECO_FUNC_SECVIO_CONFIG 26U /* Index for sc_seco_secvio_config() RPC call */ +#define SECO_FUNC_SECVIO_DGO_CONFIG 27U /* Index for sc_seco_secvio_dgo_config() RPC call */ + +/* IRQ RPC */ +#define IRQ_FUNC_UNKNOWN 0 /* Unknown function */ +#define IRQ_FUNC_ENABLE 1U /* Index for sc_irq_enable() RPC call */ +#define IRQ_FUNC_STATUS 2U /* Index for sc_irq_status() RPC call */ + +/* TIMER RPC */ +#define TIMER_FUNC_UNKNOWN 0 /* Unknown function */ +#define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */ +#define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */ +#define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */ +#define TIMER_FUNC_GET_WDOG_STATUS 5U /* Index for sc_timer_get_wdog_status() RPC call */ +#define TIMER_FUNC_PT_GET_WDOG_STATUS 13U /* Index for sc_timer_pt_get_wdog_status() RPC call */ +#define TIMER_FUNC_SET_WDOG_ACTION 10U /* Index for sc_timer_set_wdog_action() RPC call */ +#define TIMER_FUNC_SET_RTC_TIME 6U /* Index for sc_timer_set_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_TIME 7U /* Index for sc_timer_get_rtc_time() RPC call */ +#define TIMER_FUNC_GET_RTC_SEC1970 9U /* Index for sc_timer_get_rtc_sec1970() RPC call */ +#define TIMER_FUNC_SET_RTC_ALARM 8U /* Index for sc_timer_set_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_PERIODIC_ALARM 14U /* Index for sc_timer_set_rtc_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_RTC_ALARM 15U /* Index for sc_timer_cancel_rtc_alarm() RPC call */ +#define TIMER_FUNC_SET_RTC_CALB 11U /* Index for sc_timer_set_rtc_calb() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_ALARM 16U /* Index for sc_timer_set_sysctr_alarm() RPC call */ +#define TIMER_FUNC_SET_SYSCTR_PERIODIC_ALARM 17U /* Index for sc_timer_set_sysctr_periodic_alarm() RPC call */ +#define TIMER_FUNC_CANCEL_SYSCTR_ALARM 18U /* Index for sc_timer_cancel_sysctr_alarm() RPC call */ #endif /* SC_RPC_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index 14ee6f9..05f736f 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -72,6 +72,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, sc_faddr_t address); sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); +int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); /* MISC API */ int sc_misc_set_control(sc_ipc_t ipc, sc_rsrc_t resource, @@ -108,6 +109,7 @@ int sc_rm_get_resource_owner(sc_ipc_t ipc, sc_rsrc_t resource, /* PAD API */ int sc_pad_set(sc_ipc_t ipc, sc_pad_t pad, u32 val); +int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); /* SMMU API */ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); @@ -122,5 +124,13 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, sc_faddr_t export_addr, u16 max_size); +int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size); +int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock); +int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, + u16 msg_size, sc_faddr_t dst_addr, u16 dst_size); +int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); +int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, + u32 *data0, u32 *data1, u32 *data2, u32 *data3, + u32 *data4, u8 size); #endif diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h index 905c568..df368e8 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pad/api.h @@ -6,6 +6,9 @@ #ifndef SC_PAD_API_H #define SC_PAD_API_H +/* Defines for type widths */ +#define SC_PAD_MUX_W 3U /* Width of mux parameter */ + /* Defines for sc_pad_config_t */ #define SC_PAD_CONFIG_NORMAL 0U /* Normal */ #define SC_PAD_CONFIG_OD 1U /* Open Drain */ diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h index 9eadc88..adfed13 100644 --- a/arch/arm/include/asm/arch-imx8/sci/types.h +++ b/arch/arm/include/asm/arch-imx8/sci/types.h @@ -32,6 +32,7 @@ typedef u64 sc_ipc_t; #define SC_83MHZ 83333333U /* 83MHz */ #define SC_84MHZ 84375000U /* 84.37MHz */ #define SC_100MHZ 100000000U /* 100MHz */ +#define SC_114MHZ 114000000U /* 114MHz */ #define SC_125MHZ 125000000U /* 125MHz */ #define SC_133MHZ 133333333U /* 133MHz */ #define SC_135MHZ 135000000U /* 135MHz */ @@ -52,6 +53,7 @@ typedef u64 sc_ipc_t; #define SC_372MHZ 372000000U /* 372MHz */ #define SC_375MHZ 375000000U /* 375MHz */ #define SC_400MHZ 400000000U /* 400MHz */ +#define SC_465MHZ 465000000U /* 465MHz */ #define SC_500MHZ 500000000U /* 500MHz */ #define SC_594MHZ 594000000U /* 594MHz */ #define SC_625MHZ 625000000U /* 625MHz */ @@ -75,6 +77,7 @@ typedef u64 sc_ipc_t; #define SC_1500MHZ 1500000000U /* 1.5GHz */ #define SC_1600MHZ 1600000000U /* 1.6GHz */ #define SC_1800MHZ 1800000000U /* 1.8GHz */ +#define SC_1860MHZ 1860000000U /* 1.86GHz */ #define SC_2000MHZ 2000000000U /* 2.0GHz */ #define SC_2112MHZ 2112000000U /* 2.12GHz */ @@ -89,6 +92,7 @@ typedef u64 sc_ipc_t; #define SC_144MHZ 144000000U /* 144MHz */ #define SC_192MHZ 192000000U /* 192MHz */ #define SC_211MHZ 211200000U /* 211.2MHz */ +#define SC_228MHZ 228000000U /* 233MHz */ #define SC_240MHZ 240000000U /* 240MHz */ #define SC_264MHZ 264000000U /* 264MHz */ #define SC_352MHZ 352000000U /* 352MHz */ @@ -96,11 +100,13 @@ typedef u64 sc_ipc_t; #define SC_384MHZ 384000000U /* 384MHz */ #define SC_396MHZ 396000000U /* 396MHz */ #define SC_432MHZ 432000000U /* 432MHz */ +#define SC_456MHZ 456000000U /* 466MHz */ #define SC_480MHZ 480000000U /* 480MHz */ #define SC_600MHZ 600000000U /* 600MHz */ #define SC_744MHZ 744000000U /* 744MHz */ #define SC_792MHZ 792000000U /* 792MHz */ #define SC_864MHZ 864000000U /* 864MHz */ +#define SC_912MHZ 912000000U /* 912MHz */ #define SC_960MHZ 960000000U /* 960MHz */ #define SC_1056MHZ 1056000000U /* 1056MHz */ #define SC_1104MHZ 1104000000U /* 1104MHz */ diff --git a/arch/arm/include/asm/arch-imx8/snvs_security_sc.h b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h new file mode 100644 index 0000000..0b7ded7 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/snvs_security_sc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef _SNVS_SECURITY_SC_H +#define _SNVS_SECURITY_SC_H + +int snvs_security_sc_init(void); + +#endif /* _SNVS_SECURITY_SC_H */ diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h index debed6b..140e8bb 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h @@ -19,7 +19,7 @@ #define LOCK_STATUS BIT(31) #define LOCK_SEL_MASK BIT(29) -#define CLKE_MASK BIT(11) +#define CLKE_MASK BIT(13) #define RST_MASK BIT(9) #define BYPASS_MASK BIT(4) #define MDIV_SHIFT 12 @@ -363,7 +363,8 @@ enum clk_root_src { EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, - OSC_HDMI_CLK + OSC_HDMI_CLK, + ARM_A53_ALT_CLK, }; enum clk_ccgr_index { diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h index 38a6f59..9dda6dd 100644 --- a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h +++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h @@ -153,6 +153,7 @@ enum clk_root_src { EXT_CLK_3, EXT_CLK_4, OSC_27M_CLK, + ARM_A53_ALT_CLK, }; /* CCGR index */ @@ -419,7 +420,7 @@ enum clk_src_index { enum frac_pll_out_val { FRAC_PLL_OUT_1000M, - FRAC_PLL_OUT_1600M, + FRAC_PLL_OUT_800M, }; void init_nand_clk(void); diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 35b39b1..2a997f2 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -16,7 +16,7 @@ #define is_soc_rev(rev) (soc_rev() == rev) /* returns MXC_CPU_ value */ -#define cpu_type(rev) (((rev) >> 12) & 0xff) +#define cpu_type(rev) (((rev) >> 12) & 0x1ff) #define soc_type(rev) (((rev) >> 12) & 0xf0) /* both macros return/take MXC_CPU_ constants */ #define get_cpu_type() (cpu_type(get_cpu_rev())) @@ -37,13 +37,15 @@ #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) #define is_mx6solo() (is_cpu_type(MXC_CPU_MX6SOLO)) #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) -#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL) || is_cpu_type(MXC_CPU_MX6ULZ)) #define is_mx6ulz() (is_cpu_type(MXC_CPU_MX6ULZ)) #define is_mx6sll() (is_cpu_type(MXC_CPU_MX6SLL)) #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP)) -#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ)) +#define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ) || is_cpu_type(MXC_CPU_IMX8MD) || is_cpu_type(MXC_CPU_IMX8MQL)) +#define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) +#define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ @@ -53,7 +55,14 @@ #define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL)) #define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS)) #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) -#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN)) +#define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ + is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ + is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL)) +#define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) +#define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) +#define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) +#define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) +#define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 8482f54..b839aa7 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -57,7 +57,7 @@ obj-y += interrupts_64.o else obj-y += interrupts.o endif -ifndef CONFIG_SYSRESET +ifndef CONFIG_$(SPL_TPL_)SYSRESET obj-y += reset.o endif diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index bfa85c6..e83f693 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -95,7 +95,17 @@ const char *get_imx_type(u32 imxtype) case MXC_CPU_IMX8MP: return "8MP"; /* Quad-core version of the imx8mp */ case MXC_CPU_IMX8MN: - return "8MNano";/* Quad-core version of the imx8mn */ + return "8MNano Quad"; /* Quad-core version */ + case MXC_CPU_IMX8MND: + return "8MNano Dual"; /* Dual-core version */ + case MXC_CPU_IMX8MNS: + return "8MNano Solo"; /* Single-core version */ + case MXC_CPU_IMX8MNL: + return "8MNano QuadLite"; /* Quad-core Lite version */ + case MXC_CPU_IMX8MNDL: + return "8MNano DualLite"; /* Dual-core Lite version */ + case MXC_CPU_IMX8MNSL: + return "8MNano SoloLite"; /* Single-core Lite version */ case MXC_CPU_IMX8MM: return "8MMQ"; /* Quad-core version of the imx8mm */ case MXC_CPU_IMX8MML: @@ -109,7 +119,11 @@ const char *get_imx_type(u32 imxtype) case MXC_CPU_IMX8MMSL: return "8MMSL"; /* Single-core Lite version of the imx8mm */ case MXC_CPU_IMX8MQ: - return "8MQ"; /* Quad-core version of the imx8m */ + return "8MQ"; /* Quad-core version of the imx8mq */ + case MXC_CPU_IMX8MQL: + return "8MQLite"; /* Quad-core Lite version of the imx8mq */ + case MXC_CPU_IMX8MD: + return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: @@ -314,6 +328,7 @@ enum cpu_speed { OCOTP_TESTER3_SPEED_GRADE1, OCOTP_TESTER3_SPEED_GRADE2, OCOTP_TESTER3_SPEED_GRADE3, + OCOTP_TESTER3_SPEED_GRADE4, }; u32 get_cpu_speed_grade_hz(void) @@ -326,17 +341,28 @@ u32 get_cpu_speed_grade_hz(void) val = readl(&fuse->tester3); val >>= OCOTP_TESTER3_SPEED_SHIFT; - val &= 0x3; + + if (is_imx8mn() || is_imx8mp()) { + val &= 0xf; + return 2300000000 - val * 100000000; + } + + if (is_imx8mm()) + val &= 0x7; + else + val &= 0x3; switch(val) { case OCOTP_TESTER3_SPEED_GRADE0: return 800000000; case OCOTP_TESTER3_SPEED_GRADE1: - return is_mx7() ? 500000000 : 1000000000; + return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000)); case OCOTP_TESTER3_SPEED_GRADE2: - return is_mx7() ? 1000000000 : 1300000000; + return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000)); case OCOTP_TESTER3_SPEED_GRADE3: - return is_mx7() ? 1200000000 : 1500000000; + return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000)); + case OCOTP_TESTER3_SPEED_GRADE4: + return 2000000000; } return 0; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 5827ab3..1f8add0 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -90,4 +90,17 @@ source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" source "board/siemens/capricorn/Kconfig" +config IMX_SNVS_SEC_SC + bool "Support SNVS configuration" + help + Allow to configure the SNVS via SCU API to configure tampers and secure + violation. + +config IMX_SNVS_SEC_SC_AUTO + bool "Support SNVS configuration command" + depends on IMX_SNVS_SEC_SC + help + This configuration will apply the selected configurations automatically + at boot. + endif diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index 7ffb7e9..bbb41ad 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_AHAB_BOOT) += ahab.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o endif +obj-$(CONFIG_IMX_SNVS_SEC_SC) += snvs_security_sc.o diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index cf3c7d7..6d25abe 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -75,7 +75,7 @@ int authenticate_os_container(ulong addr) memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)addr, ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); - err = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER, + err = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); if (err) { printf("Authenticate container hdr failed, return %d\n", @@ -90,22 +90,21 @@ int authenticate_os_container(ulong addr) sizeof(struct container_hdr) + i * sizeof(struct boot_img_t)); - debug("img %d, dst 0x%llx, src 0x%lx, size 0x%x\n", - i, img->dst, img->offset + addr, img->size); + debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n", + i, (uint32_t) img->dst, img->offset + addr, img->size); memcpy((void *)img->dst, (const void *)(img->offset + addr), img->size); s = img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1); - e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE); + e = ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1; flush_dcache_range(s, e); /* Find the memreg and set permission for seco pt */ err = sc_rm_find_memreg(-1, &mr, s, e); if (err) { - printf("Not found memreg for image: %d, error %d\n", - i, err); + printf("Error: can't find memreg for image load address 0x%x, error %d\n", img->dst, err); ret = -ENOMEM; goto exit; } @@ -123,7 +122,7 @@ int authenticate_os_container(ulong addr) goto exit; } - err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE, + err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, (1 << i)); if (err) { printf("Authenticate img %d failed, return %d\n", @@ -144,7 +143,7 @@ int authenticate_os_container(ulong addr) } exit: - if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0) != SC_ERR_NONE) + if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0) != SC_ERR_NONE) printf("Error: release container failed!\n"); return ret; diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index 00fe467..76d6571 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -2,6 +2,7 @@ #include <common.h> #include <asm/arch/sci/sci.h> #include <asm/mach-imx/sys_proto.h> +#include <imx_sip.h> int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate) { @@ -26,9 +27,6 @@ int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate) return 0; } -#define FSL_SIP_BUILDINFO 0xC2000003 -#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00 - void build_info(void) { u32 seco_build = 0, seco_commit = 0; @@ -51,8 +49,8 @@ void build_info(void) } /* Get ARM Trusted Firmware commit id */ - atf_commit = call_imx_sip(FSL_SIP_BUILDINFO, - FSL_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); + atf_commit = call_imx_sip(IMX_SIP_BUILDINFO, + IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); if (atf_commit == 0xffffffff) { debug("ATF does not support build info\n"); atf_commit = 0x30; /* Display 0 */ diff --git a/arch/arm/mach-imx/imx8/parse-container.c b/arch/arm/mach-imx/imx8/parse-container.c index b57e68e..cc8a51a 100644 --- a/arch/arm/mach-imx/imx8/parse-container.c +++ b/arch/arm/mach-imx/imx8/parse-container.c @@ -23,23 +23,23 @@ static int authenticate_image(struct boot_img_t *img, int image_index) int err; int ret = 0; - debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n", - image_index, img->dst, img->offset, img->size); + debug("img %d, dst 0x%x, src 0x%x, size 0x%x\n", + image_index, (uint32_t)img->dst, img->offset, img->size); /* Find the memreg and set permission for seco pt */ err = sc_rm_find_memreg(-1, &mr, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), - ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE)); + ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE) - 1); if (err) { - printf("can't find memreg for image: %d, err %d\n", - image_index, err); + printf("can't find memreg for image %d load address 0x%x, error %d\n", + image_index, img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1), err); return -ENOMEM; } err = sc_rm_get_memreg_info(-1, mr, &start, &end); if (!err) - debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); + debug("memreg %u 0x%x -- 0x%x\n", mr, start, end); err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, SC_RM_PERM_FULL); @@ -49,7 +49,7 @@ static int authenticate_image(struct boot_img_t *img, int image_index) return -EPERM; } - err = sc_seco_authenticate(-1, SC_MISC_VERIFY_IMAGE, + err = sc_seco_authenticate(-1, SC_SECO_VERIFY_IMAGE, 1 << image_index); if (err) { printf("authenticate img %d failed, return %d\n", @@ -168,7 +168,7 @@ static int read_auth_container(struct spl_image_info *spl_image, memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container, ALIGN(length, CONFIG_SYS_CACHELINE_SIZE)); - ret = sc_seco_authenticate(-1, SC_MISC_AUTH_CONTAINER, + ret = sc_seco_authenticate(-1, SC_SECO_AUTH_CONTAINER, SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); if (ret) { printf("authenticate container hdr failed, return %d\n", ret); @@ -194,7 +194,7 @@ static int read_auth_container(struct spl_image_info *spl_image, end_auth: #ifdef CONFIG_AHAB_BOOT - if (sc_seco_authenticate(-1, SC_MISC_REL_CONTAINER, 0)) + if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) printf("Error: release container failed!\n"); #endif return ret; diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c new file mode 100644 index 0000000..73f5651 --- /dev/null +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -0,0 +1,923 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2020 NXP. + */ + +/* + * Configuration of the Tamper pins in different mode: + * - default (no tamper pins): _default_ + * - passive mode expecting VCC on the line: "_passive_vcc_" + * - passive mode expecting VCC on the line: "_passive_gnd_" + * - active mode: "_active_" + */ + +#include <command.h> +#include <log.h> +#include <stddef.h> +#include <common.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch-imx8/imx8-pins.h> +#include <asm/arch-imx8/snvs_security_sc.h> + +/* Access to gd */ +DECLARE_GLOBAL_DATA_PTR; + +#define SC_WRITE_CONF 1 + +#define PGD_HEX_VALUE 0x41736166 +#define SRTC_EN 0x1 +#define DP_EN BIT(5) + +struct snvs_security_sc_conf { + struct snvs_hp_conf { + u32 lock; /* HPLR - HP Lock */ + u32 __cmd; /* HPCOMR - HP Command */ + u32 __ctl; /* HPCR - HP Control */ + u32 secvio_intcfg; /* HPSICR - Security Violation Int + * Config + */ + u32 secvio_ctl; /* HPSVCR - Security Violation Control*/ + u32 status; /* HPSR - HP Status */ + u32 secvio_status; /* HPSVSR - Security Violation Status */ + u32 __ha_counteriv; /* High Assurance Counter IV */ + u32 __ha_counter; /* High Assurance Counter */ + u32 __rtc_msb; /* Real Time Clock/Counter MSB */ + u32 __rtc_lsb; /* Real Time Counter LSB */ + u32 __time_alarm_msb; /* Time Alarm MSB */ + u32 __time_alarm_lsb; /* Time Alarm LSB */ + } hp; + struct snvs_lp_conf { + u32 lock; + u32 __ctl; + u32 __mstr_key_ctl; /* Master Key Control */ + u32 secvio_ctl; /* Security Violation Control */ + u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration*/ + u32 tamper_det_cfg; /* Tamper Detectors Configuration */ + u32 status; + u32 __srtc_msb; /* Secure Real Time Clock/Counter MSB */ + u32 __srtc_lsb; /* Secure Real Time Clock/Counter LSB */ + u32 __time_alarm; /* Time Alarm */ + u32 __smc_msb; /* Secure Monotonic Counter MSB */ + u32 __smc_lsb; /* Secure Monotonic Counter LSB */ + u32 __pwr_glitch_det; /* Power Glitch Detector */ + u32 __gen_purpose; + u8 __zmk[32]; /* Zeroizable Master Key */ + u32 __rsvd0; + u32 __gen_purposes[4]; /* gp0_30 to gp0_33 */ + u32 tamper_det_cfg2; /* Tamper Detectors Configuration2 */ + u32 tamper_det_status; /* Tamper Detectors status */ + u32 tamper_filt1_cfg; /* Tamper Glitch Filter1 Configuration*/ + u32 tamper_filt2_cfg; /* Tamper Glitch Filter2 Configuration*/ + u32 __rsvd1[4]; + u32 act_tamper1_cfg; /* Active Tamper1 Configuration */ + u32 act_tamper2_cfg; /* Active Tamper2 Configuration */ + u32 act_tamper3_cfg; /* Active Tamper3 Configuration */ + u32 act_tamper4_cfg; /* Active Tamper4 Configuration */ + u32 act_tamper5_cfg; /* Active Tamper5 Configuration */ + u32 __rsvd2[3]; + u32 act_tamper_ctl; /* Active Tamper Control */ + u32 act_tamper_clk_ctl; /* Active Tamper Clock Control */ + u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */ + u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */ + } lp; +}; + +static struct snvs_security_sc_conf snvs_default_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_ctl = 0x3000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x76, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static struct snvs_security_sc_conf snvs_passive_vcc_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_ctl = 0x3000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x276, /* ET1 will trig on line at GND + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static struct snvs_security_sc_conf snvs_passive_gnd_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_ctl = 0x3000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static struct snvs_security_sc_conf snvs_active_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_ctl = 0x3000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0x00800000, /* Enable filtering */ + .tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0x84001111, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0x00010001, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0x1, + .act_tamper_routing_ctl2 = 0, + } +}; + +static struct snvs_security_sc_conf *get_snvs_config(void) +{ + return &snvs_default_config; +} + +struct snvs_dgo_conf { + u32 tamper_offset_ctl; + u32 tamper_pull_ctl; + u32 tamper_ana_test_ctl; + u32 tamper_sensor_trim_ctl; + u32 tamper_misc_ctl; + u32 tamper_core_volt_mon_ctl; +}; + +static struct snvs_dgo_conf snvs_dgo_default_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static struct snvs_dgo_conf snvs_dgo_passive_vcc_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000001, /* Pull down ET1 */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static struct snvs_dgo_conf snvs_dgo_passive_gnd_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000401, /* Pull up ET1 */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static struct snvs_dgo_conf snvs_dgo_active_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static struct snvs_dgo_conf *get_snvs_dgo_config(void) +{ + return &snvs_dgo_default_config; +} + +struct tamper_pin_cfg { + u32 pad; + u32 mux_conf; +}; + +static struct tamper_pin_cfg tamper_pin_list_default_config[] = { + {SC_P_CSI_D00, 0}, /* Tamp_Out0 */ + {SC_P_CSI_D01, 0}, /* Tamp_Out1 */ + {SC_P_CSI_D02, 0}, /* Tamp_Out2 */ + {SC_P_CSI_D03, 0}, /* Tamp_Out3 */ + {SC_P_CSI_D04, 0}, /* Tamp_Out4 */ + {SC_P_CSI_D05, 0}, /* Tamp_In0 */ + {SC_P_CSI_D06, 0}, /* Tamp_In1 */ + {SC_P_CSI_D07, 0}, /* Tamp_In2 */ + {SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */ + {SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */ +}; + +static struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = { + {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ +}; + +static struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = { + {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ +}; + +static struct tamper_pin_cfg tamper_pin_list_active_config[] = { + {SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */ + {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ +}; + +#define TAMPER_PIN_LIST_CHOSEN tamper_pin_list_default_config + +static struct tamper_pin_cfg *get_tamper_pin_cfg_list(u32 *size) +{ + *size = sizeof(TAMPER_PIN_LIST_CHOSEN) / + sizeof(TAMPER_PIN_LIST_CHOSEN[0]); + + return TAMPER_PIN_LIST_CHOSEN; +} + +#define SC_CONF_OFFSET_OF(_field) \ + (offsetof(struct snvs_security_sc_conf, _field)) + +static u32 ptr_value(u32 *_p) +{ + return (_p) ? *_p : 0xdeadbeef; +} + +static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, + u32 *_p3, u32 *_p4, u32 *_p5, + u32 _cnt) +{ + int scierr = 0; + u32 d1 = ptr_value(_p1); + u32 d2 = ptr_value(_p2); + u32 d3 = ptr_value(_p3); + u32 d4 = ptr_value(_p4); + u32 d5 = ptr_value(_p5); + + scierr = sc_seco_secvio_config(-1, id, SC_WRITE_CONF, &d1, &d2, &d3, + &d4, &d4, _cnt); + if (scierr != SC_ERR_NONE) { + printf("Failed to set secvio configuration\n"); + debug("Failed to set conf id 0x%x with values ", id); + debug("0x%.8x 0x%.8x 0x%.8x 0x%.8x 0x%.8x (cnt: %d)\n", + d1, d2, d3, d4, d5, _cnt); + goto exit; + } + + if (_p1) + *(u32 *)_p1 = d1; + if (_p2) + *(u32 *)_p2 = d2; + if (_p3) + *(u32 *)_p3 = d3; + if (_p4) + *(u32 *)_p4 = d4; + if (_p5) + *(u32 *)_p5 = d5; + +exit: + return scierr; +} + +#define SC_CHECK_WRITE1(id, _p1) \ + check_write_secvio_config(id, _p1, NULL, NULL, NULL, NULL, 1) + +static int apply_snvs_config(struct snvs_security_sc_conf *cnf) +{ + int scierr = 0; + + debug("%s\n", __func__); + + debug("Applying config:\n" + "\thp.lock = 0x%.8x\n" + "\thp.secvio_ctl = 0x%.8x\n" + "\tlp.lock = 0x%.8x\n" + "\tlp.secvio_ctl = 0x%.8x\n" + "\tlp.tamper_filt_cfg = 0x%.8x\n" + "\tlp.tamper_det_cfg = 0x%.8x\n" + "\tlp.tamper_det_cfg2 = 0x%.8x\n" + "\tlp.tamper_filt1_cfg = 0x%.8x\n" + "\tlp.tamper_filt2_cfg = 0x%.8x\n" + "\tlp.act_tamper1_cfg = 0x%.8x\n" + "\tlp.act_tamper2_cfg = 0x%.8x\n" + "\tlp.act_tamper3_cfg = 0x%.8x\n" + "\tlp.act_tamper4_cfg = 0x%.8x\n" + "\tlp.act_tamper5_cfg = 0x%.8x\n" + "\tlp.act_tamper_ctl = 0x%.8x\n" + "\tlp.act_tamper_clk_ctl = 0x%.8x\n" + "\tlp.act_tamper_routing_ctl1 = 0x%.8x\n" + "\tlp.act_tamper_routing_ctl2 = 0x%.8x\n", + cnf->hp.lock, + cnf->hp.secvio_ctl, + cnf->lp.lock, + cnf->lp.secvio_ctl, + cnf->lp.tamper_filt_cfg, + cnf->lp.tamper_det_cfg, + cnf->lp.tamper_det_cfg2, + cnf->lp.tamper_filt1_cfg, + cnf->lp.tamper_filt2_cfg, + cnf->lp.act_tamper1_cfg, + cnf->lp.act_tamper2_cfg, + cnf->lp.act_tamper3_cfg, + cnf->lp.act_tamper4_cfg, + cnf->lp.act_tamper5_cfg, + cnf->lp.act_tamper_ctl, + cnf->lp.act_tamper_clk_ctl, + cnf->lp.act_tamper_routing_ctl1, + cnf->lp.act_tamper_routing_ctl2); + + scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_filt_cfg), + &cnf->lp.tamper_filt_cfg, + &cnf->lp.tamper_filt1_cfg, + &cnf->lp.tamper_filt2_cfg, NULL, + NULL, 3); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Configure AT */ + scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg), + &cnf->lp.act_tamper1_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, + &cnf->lp.act_tamper2_cfg, 5); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Configure AT routing */ + scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper_routing_ctl1), + &cnf->lp.act_tamper_routing_ctl1, + &cnf->lp.act_tamper_routing_ctl2, + NULL, NULL, NULL, 2); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Configure AT frequency */ + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_clk_ctl), + &cnf->lp.act_tamper_clk_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Activate the ATs */ + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.act_tamper_ctl), + &cnf->lp.act_tamper_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Activate the detectors */ + scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_cfg), + &cnf->lp.tamper_det_cfg, + &cnf->lp.tamper_det_cfg2, NULL, NULL, + NULL, 2); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Configure LP secvio */ + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.secvio_ctl), + &cnf->lp.secvio_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Configure HP secvio */ + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_ctl), + &cnf->hp.secvio_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Lock access */ + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock); + if (scierr != SC_ERR_NONE) + goto exit; + + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock); + if (scierr != SC_ERR_NONE) + goto exit; + +exit: + return (scierr == SC_ERR_NONE) ? 0 : -EIO; +} + +static int dgo_write(u32 _id, u8 _access, u32 *_pdata) +{ + int scierr = sc_seco_secvio_dgo_config(-1, _id, _access, _pdata); + + if (scierr != SC_ERR_NONE) { + printf("Failed to set dgo configuration\n"); + debug("Failed to set conf id 0x%x : 0x%.8x", _id, *_pdata); + } + + return scierr; +} + +static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf) +{ + int scierr = 0; + + debug("%s\n", __func__); + + debug("Applying config:\n" + "\ttamper_offset_ctl = 0x%.8x\n" + "\ttamper_pull_ctl = 0x%.8x\n" + "\ttamper_ana_test_ctl = 0x%.8x\n" + "\ttamper_sensor_trim_ctl = 0x%.8x\n" + "\ttamper_misc_ctl = 0x%.8x\n" + "\ttamper_core_volt_mon_ctl = 0x%.8x\n", + cnf->tamper_offset_ctl, + cnf->tamper_pull_ctl, + cnf->tamper_ana_test_ctl, + cnf->tamper_sensor_trim_ctl, + cnf->tamper_misc_ctl, + cnf->tamper_core_volt_mon_ctl); + + dgo_write(0x04, 1, &cnf->tamper_offset_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + dgo_write(0x14, 1, &cnf->tamper_pull_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + + /* Last as it could lock the writes */ + dgo_write(0x44, 1, &cnf->tamper_misc_ctl); + if (scierr != SC_ERR_NONE) + goto exit; + +exit: + return (scierr == SC_ERR_NONE) ? 0 : -EIO; +} + +static int pad_write(u32 _pad, u32 _value) +{ + int scierr = sc_pad_set(-1, _pad, _value); + + if (scierr != SC_ERR_NONE) { + printf("Failed to set pad configuration\n"); + debug("Failed to set conf pad 0x%x : 0x%.8x", _pad, _value); + } + + return scierr; +} + +static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) +{ + int scierr = 0; + u32 idx; + + debug("%s\n", __func__); + + for (idx = 0; idx < size; idx++) { + debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad, + confs[idx].mux_conf); + pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); + if (scierr != SC_ERR_NONE) + goto exit; + } + +exit: + return (scierr == SC_ERR_NONE) ? 0 : -EIO; +} + +int examples(void) +{ + u32 size; + struct snvs_security_sc_conf *snvs_conf; + struct snvs_dgo_conf *snvs_dgo_conf; + struct tamper_pin_cfg *tamper_pin_conf; + + /* Caller */ + snvs_conf = get_snvs_config(); + snvs_dgo_conf = get_snvs_dgo_config(); + tamper_pin_conf = get_tamper_pin_cfg_list(&size); + + /* Default */ + snvs_conf = &snvs_default_config; + snvs_dgo_conf = &snvs_dgo_default_config; + tamper_pin_conf = tamper_pin_list_default_config; + + /* Passive tamper expecting VCC on the line */ + snvs_conf = &snvs_passive_vcc_config; + snvs_dgo_conf = &snvs_dgo_passive_vcc_config; + tamper_pin_conf = tamper_pin_list_passive_vcc_config; + + /* Passive tamper expecting GND on the line */ + snvs_conf = &snvs_passive_gnd_config; + snvs_dgo_conf = &snvs_dgo_passive_gnd_config; + tamper_pin_conf = tamper_pin_list_passive_gnd_config; + + /* Active tamper */ + snvs_conf = &snvs_active_config; + snvs_dgo_conf = &snvs_dgo_active_config; + tamper_pin_conf = tamper_pin_list_active_config; + + return !snvs_conf + !snvs_dgo_conf + !tamper_pin_conf; +} + +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO +int snvs_security_sc_init(void) +{ + int err = 0; + + struct snvs_security_sc_conf *snvs_conf; + struct snvs_dgo_conf *snvs_dgo_conf; + struct tamper_pin_cfg *tamper_pin_conf; + u32 size; + + debug("%s\n", __func__); + + snvs_conf = get_snvs_config(); + snvs_dgo_conf = get_snvs_dgo_config(); + + tamper_pin_conf = get_tamper_pin_cfg_list(&size); + + err = apply_tamper_pin_list_config(tamper_pin_conf, size); + if (err) { + debug("Failed to set pins\n"); + goto exit; + } + + err = apply_snvs_dgo_config(snvs_dgo_conf); + if (err) { + debug("Failed to set dgo\n"); + goto exit; + } + + err = apply_snvs_config(snvs_conf); + if (err) { + debug("Failed to set snvs\n"); + goto exit; + } + +exit: + return err; +} +#endif /* CONFIG_IMX_SNVS_SEC_SC_AUTO */ + +static char snvs_cfg_help_text[] = + "snvs_cfg\n" + "\thp.lock\n" + "\thp.secvio_ctl\n" + "\tlp.lock\n" + "\tlp.secvio_ctl\n" + "\tlp.tamper_filt_cfg\n" + "\tlp.tamper_det_cfg\n" + "\tlp.tamper_det_cfg2\n" + "\tlp.tamper_filt1_cfg\n" + "\tlp.tamper_filt2_cfg\n" + "\tlp.act_tamper1_cfg\n" + "\tlp.act_tamper2_cfg\n" + "\tlp.act_tamper3_cfg\n" + "\tlp.act_tamper4_cfg\n" + "\tlp.act_tamper5_cfg\n" + "\tlp.act_tamper_ctl\n" + "\tlp.act_tamper_clk_ctl\n" + "\tlp.act_tamper_routing_ctl1\n" + "\tlp.act_tamper_routing_ctl2\n" + "\n" + "ALL values should be in hexadecimal format"; + +#define NB_REGISTERS 18 +static int do_snvs_cfg(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int err = 0; + u32 idx = 0; + + struct snvs_security_sc_conf conf = {0}; + + if (argc != (NB_REGISTERS + 1)) + return CMD_RET_USAGE; + + conf.hp.lock = simple_strtoul(argv[++idx], NULL, 16); + conf.hp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.lock = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.tamper_filt_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.tamper_det_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.tamper_det_cfg2 = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.tamper_filt1_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.tamper_filt2_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper1_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper2_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper3_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper4_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper5_cfg = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper_clk_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper_routing_ctl1 = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.act_tamper_routing_ctl2 = simple_strtoul(argv[++idx], NULL, 16); + + err = apply_snvs_config(&conf); + + return err; +} + +U_BOOT_CMD(snvs_cfg, + NB_REGISTERS + 1, 1, do_snvs_cfg, + "Security violation configuration", + snvs_cfg_help_text +); + +static char snvs_dgo_cfg_help_text[] = + "snvs_dgo_cfg\n" + "\ttamper_offset_ctl\n" + "\ttamper_pull_ctl\n" + "\ttamper_ana_test_ctl\n" + "\ttamper_sensor_trim_ctl\n" + "\ttamper_misc_ctl\n" + "\ttamper_core_volt_mon_ctl\n" + "\n" + "ALL values should be in hexadecimal format"; + +static int do_snvs_dgo_cfg(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err = 0; + u32 idx = 0; + + struct snvs_dgo_conf conf = {0}; + + if (argc != (6 + 1)) + return CMD_RET_USAGE; + + conf.tamper_offset_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.tamper_pull_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.tamper_ana_test_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.tamper_sensor_trim_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.tamper_misc_ctl = simple_strtoul(argv[++idx], NULL, 16); + conf.tamper_core_volt_mon_ctl = simple_strtoul(argv[++idx], NULL, 16); + + err = apply_snvs_dgo_config(&conf); + + return err; +} + +U_BOOT_CMD(snvs_dgo_cfg, + 7, 1, do_snvs_dgo_cfg, + "SNVS DGO configuration", + snvs_dgo_cfg_help_text +); + +static char tamper_pin_cfg_help_text[] = + "snvs_dgo_cfg\n" + "\tpad\n" + "\tvalue\n" + "\n" + "ALL values should be in hexadecimal format"; + +static int do_tamper_pin_cfg(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err = 0; + u32 idx = 0; + + struct tamper_pin_cfg conf = {0}; + + if (argc != (2 + 1)) + return CMD_RET_USAGE; + + conf.pad = simple_strtoul(argv[++idx], NULL, 10); + conf.mux_conf = simple_strtoul(argv[++idx], NULL, 16); + + err = apply_tamper_pin_list_config(&conf, 1); + + return err; +} + +U_BOOT_CMD(tamper_pin_cfg, + 3, 1, do_tamper_pin_cfg, + "tamper pin configuration", + tamper_pin_cfg_help_text +); + +static char snvs_clear_status_help_text[] = + "snvs_clear_status\n" + "\tHPSR\n" + "\tHPSVSR\n" + "\tLPSR\n" + "\tLPTDSR\n" + "\n" + "Write the status registers with the value provided," + " clearing the status"; + +static int do_snvs_clear_status(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int scierr = 0; + u32 idx = 0; + + struct snvs_security_sc_conf conf = {0}; + + if (argc != (2 + 1)) + return CMD_RET_USAGE; + + conf.lp.status = simple_strtoul(argv[++idx], NULL, 16); + conf.lp.tamper_det_status = simple_strtoul(argv[++idx], NULL, 16); + + scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.status), + &conf.lp.status, NULL, NULL, NULL, + NULL, 1); + if (scierr != SC_ERR_NONE) + goto exit; + + scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.tamper_det_status), + &conf.lp.tamper_det_status, NULL, + NULL, NULL, NULL, 1); + if (scierr != SC_ERR_NONE) + goto exit; + +exit: + return (scierr == SC_ERR_NONE) ? 0 : 1; +} + +U_BOOT_CMD(snvs_clear_status, + 3, 1, do_snvs_clear_status, + "snvs clear status", + snvs_clear_status_help_text +); + +static char snvs_sec_status_help_text[] = + "snvs_sec_status\n" + "Display information about the security related to tamper and secvio"; + +static int do_snvs_sec_status(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int scierr; + u32 idx; + + u32 data[5]; + + u32 pads[] = { + SC_P_CSI_D00, + SC_P_CSI_D01, + SC_P_CSI_D02, + SC_P_CSI_D03, + SC_P_CSI_D04, + SC_P_CSI_D05, + SC_P_CSI_D06, + SC_P_CSI_D07, + SC_P_CSI_HSYNC, + SC_P_CSI_VSYNC, + }; + + u32 fuses[] = { + 14, + 30, + 31, + 260, + 261, + 262, + 263, + 768, + }; + + struct snvs_reg { + u32 id; + u32 nb; + } snvs[] = { + /* Locks */ + {0x0, 1}, + {0x34, 1}, + /* Security violation */ + {0xc, 1}, + {0x10, 1}, + {0x18, 1}, + {0x40, 1}, + /* Temper detectors */ + {0x48, 2}, + {0x4c, 1}, + {0xa4, 1}, + /* */ + {0x44, 3}, + {0xe0, 1}, + {0xe4, 1}, + {0xe8, 2}, + /* Misc */ + {0x3c, 1}, + {0x5c, 2}, + {0x64, 1}, + {0xf8, 2}, + }; + + u32 dgo[] = { + 0x0, + 0x10, + 0x20, + 0x30, + 0x40, + 0x50, + }; + + /* Pins */ + printf("Pins:\n"); + for (idx = 0; idx < ARRAY_SIZE(pads); idx++) { + u8 pad_id = pads[idx]; + + scierr = sc_pad_get(-1, pad_id, &data[0]); + if (scierr == 0) + printf("\t- Pin %d: %.8x\n", pad_id, data[0]); + else + printf("Failed to read Pin %d\n", pad_id); + } + + /* Fuses */ + printf("Fuses:\n"); + for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) { + u32 fuse_id = fuses[idx]; + + scierr = sc_misc_otp_fuse_read(-1, fuse_id, &data[0]); + if (scierr == 0) + printf("\t- Fuse %d: %.8x\n", fuse_id, data[0]); + else + printf("Failed to read Fuse %d\n", fuse_id); + } + + /* SNVS */ + printf("SNVS:\n"); + for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) { + struct snvs_reg *reg = &snvs[idx]; + + scierr = sc_seco_secvio_config(-1, reg->id, 0, &data[0], + &data[1], &data[2], &data[3], + &data[4], reg->nb); + if (scierr == 0) { + int subidx; + + printf("\t- SNVS %.2x(%d):", reg->id, reg->nb); + for (subidx = 0; subidx < reg->nb; subidx++) + printf(" %.8x", data[subidx]); + printf("\n"); + } else { + printf("Failed to read SNVS %d\n", reg->id); + } + } + + /* DGO */ + printf("DGO:\n"); + for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) { + u8 dgo_id = dgo[idx]; + + scierr = sc_seco_secvio_dgo_config(-1, dgo_id, 0, &data[0]); + if (scierr == 0) + printf("\t- DGO %.2x: %.8x\n", dgo_id, data[0]); + else + printf("Failed to read DGO %d\n", dgo_id); + } + + return 0; +} + +U_BOOT_CMD(snvs_sec_status, + 1, 1, do_snvs_sec_status, + "tamper pin configuration", + snvs_sec_status_help_text +); diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 58f1758..895f903 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -32,6 +32,11 @@ config TARGET_IMX8MQ_EVK select IMX8MQ select IMX8M_LPDDR4 +config TARGET_IMX8MQ_PHANBELL + bool "imx8mq_phanbell" + select IMX8MQ + select IMX8M_LPDDR4 + config TARGET_IMX8MM_EVK bool "imx8mm LPDDR4 EVK board" select IMX8MM @@ -62,6 +67,7 @@ source "board/freescale/imx8mq_evk/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" +source "board/google/imx8mq_phanbell/Kconfig" source "board/toradex/verdin-imx8mm/Kconfig" endif diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index c423ac0..91c827f 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -447,34 +447,34 @@ static u32 decode_fracpll(enum clk_root_src frac_pll) } /* Only support SYS_XTAL 24M, PAD_CLK not take into consideration */ - if ((pll_gnrl_ctl & INTPLL_REF_CLK_SEL_MASK) != 0) + if ((pll_gnrl_ctl & GENMASK(1, 0)) != 0) return 0; - if ((pll_gnrl_ctl & INTPLL_RST_MASK) == 0) + if ((pll_gnrl_ctl & RST_MASK) == 0) return 0; /* * When BYPASS is equal to 1, PLL enters the bypass mode * regardless of the values of RESETB */ - if (pll_gnrl_ctl & INTPLL_BYPASS_MASK) + if (pll_gnrl_ctl & BYPASS_MASK) return 24000000u; - if (!(pll_gnrl_ctl & INTPLL_LOCK_MASK)) { + if (!(pll_gnrl_ctl & LOCK_STATUS)) { puts("pll not locked\n"); return 0; } - if (!(pll_gnrl_ctl & INTPLL_CLKE_MASK)) + if (!(pll_gnrl_ctl & CLKE_MASK)) return 0; - main_div = (pll_fdiv_ctl0 & INTPLL_MAIN_DIV_MASK) >> - INTPLL_MAIN_DIV_SHIFT; - pre_div = (pll_fdiv_ctl0 & INTPLL_PRE_DIV_MASK) >> - INTPLL_PRE_DIV_SHIFT; - post_div = (pll_fdiv_ctl0 & INTPLL_POST_DIV_MASK) >> - INTPLL_POST_DIV_SHIFT; + main_div = (pll_fdiv_ctl0 & MDIV_MASK) >> + MDIV_SHIFT; + pre_div = (pll_fdiv_ctl0 & PDIV_MASK) >> + PDIV_SHIFT; + post_div = (pll_fdiv_ctl0 & SDIV_MASK) >> + SDIV_SHIFT; - k = pll_fdiv_ctl1 & GENMASK(15, 0); + k = pll_fdiv_ctl1 & KDIV_MASK; return lldiv((main_div * 65536 + k) * 24000000ULL, 65536 * pre_div * (1 << post_div)); @@ -578,3 +578,52 @@ u32 mxc_get_clock(enum mxc_clock clk) return 0; } + +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type) +{ + u32 target; + u32 enet1_ref; + + switch (type) { + case ENET_125MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + break; + case ENET_50MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + break; + case ENET_25MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + break; + default: + return -EINVAL; + } + + /* disable the clock first */ + clock_enable(CCGR_ENET1, 0); + clock_enable(CCGR_SIM_ENET, 0); + + /* set enet axi clock 266Mhz */ + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_AXI_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet1_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_REF_CLK_ROOT, target); + + target = CLK_ROOT_ON | + ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET_TIMER_CLK_ROOT, target); + + /* enable clock */ + clock_enable(CCGR_SIM_ENET, 1); + clock_enable(CCGR_ENET1, 1); + + return 0; +} +#endif diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index aad9cf1..ee18cde 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -15,6 +15,8 @@ static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; +static u32 get_root_clk(enum clk_root_index clock_id); + static u32 decode_frac_pll(enum clk_root_src frac_pll) { u32 pll_cfg0, pll_cfg1, pllout; @@ -275,6 +277,8 @@ static u32 get_root_src_clk(enum clk_root_src root_src) case SYSTEM_PLL2_50M_CLK: case SYSTEM_PLL3_CLK: return decode_sscg_pll(root_src); + case ARM_A53_ALT_CLK: + return get_root_clk(ARM_A53_CLK_ROOT); default: return 0; } @@ -322,13 +326,26 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) return 0; } +u32 get_arm_core_clk(void) +{ + enum clk_root_src root_src; + u32 root_src_clk; + + if (clock_get_src(CORE_SEL_CFG, &root_src) < 0) + return 0; + + root_src_clk = get_root_src_clk(root_src); + + return root_src_clk; +} + unsigned int mxc_get_clock(enum mxc_clock clk) { u32 val; - switch(clk) { + switch (clk) { case MXC_ARM_CLK: - return get_root_clk(ARM_A53_CLK_ROOT); + return get_arm_core_clk(); case MXC_IPG_CLK: clock_get_target_val(IPG_CLK_ROOT, &val); val = val & 0x3; @@ -428,15 +445,13 @@ void init_clk_usdhc(u32 index) case 0: clock_enable(CCGR_USDHC1, 0); clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + CLK_ROOT_SOURCE_SEL(1)); clock_enable(CCGR_USDHC1, 1); return; case 1: clock_enable(CCGR_USDHC2, 0); clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + CLK_ROOT_SOURCE_SEL(1)); clock_enable(CCGR_USDHC2, 1); return; default: @@ -639,7 +654,7 @@ void dram_pll_init(ulong pll_val) static int frac_pll_init(u32 pll, enum frac_pll_out_val val) { void __iomem *pll_cfg0, __iomem *pll_cfg1; - u32 val_cfg0, val_cfg1; + u32 val_cfg0, val_cfg1, divq; int ret; switch (pll) { @@ -647,14 +662,17 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val) pll_cfg0 = &ana_pll->arm_pll_cfg0; pll_cfg1 = &ana_pll->arm_pll_cfg1; - if (val == FRAC_PLL_OUT_1000M) + if (val == FRAC_PLL_OUT_1000M) { val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49); - else + divq = 0; + } else { val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79); + divq = 1; + } val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK | FRAC_PLL_REFCLK_DIV_VAL(4) | - FRAC_PLL_OUTPUT_DIV_VAL(0); + FRAC_PLL_OUTPUT_DIV_VAL(divq); break; default: return -EINVAL; @@ -690,17 +708,14 @@ int clock_init(void) * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial */ grade = get_cpu_temp_grade(NULL, NULL); - if (!grade) { + if (!grade) frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M); - clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); - } else { - frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M); - clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); - } + else + frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_800M); + + /* Bypass CCM A53 ROOT, Switch to ARM PLL -> MUX-> CPU */ + clock_set_target_val(CORE_SEL_CFG, CLK_ROOT_SOURCE_SEL(1)); + /* * According to ANAMIX SPEC * sys pll1 fixed at 800MHz @@ -747,6 +762,8 @@ static int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, freq = decode_frac_pll(ARM_PLL_CLK); printf("ARM_PLL %8d MHz\n", freq / 1000000); + freq = decode_sscg_pll(DRAM_PLL1_CLK); + printf("DRAM_PLL %8d MHz\n", freq / 1000000); freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK); printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000); freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK); diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c index 8b7a4da..b5ed27a 100644 --- a/arch/arm/mach-imx/imx8m/clock_slice.c +++ b/arch/arm/mach-imx/imx8m/clock_slice.c @@ -472,33 +472,111 @@ static struct clk_root_map root_array[] = { {DRAM_PLL1_CLK} }, {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0, - {DRAM_PLL1_CLK} + {ARM_A53_ALT_CLK, ARM_PLL_CLK} }, }; -#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) +#elif defined(CONFIG_IMX8MM) static struct clk_root_map root_array[] = { {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK} }, + {ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2, + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK} + }, + {GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3, + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4, + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK} + }, + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK} }, + {VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4, + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_4} + }, + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_3} + }, + {DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + EXT_CLK_2, EXT_CLK_3} + }, + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10, {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} }, -#ifdef CONFIG_IMX8MM {NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11, {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} }, -#endif + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0, {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK, @@ -509,6 +587,146 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} }, + {VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2, + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, + {VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3, + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, + {DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4, + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK} + }, + {DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5, + {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK} + }, + {PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6, + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK} + }, + {PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + SYSTEM_PLL1_400M_CLK} + }, + {PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK} + }, + {DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9, + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10, + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2} + }, + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2} + }, + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4} + }, + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + VIDEO_PLL_CLK} + }, + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21, + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK} + }, + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30, {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, @@ -529,19 +747,546 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} }, + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34, + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35, + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36, {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK, EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} }, + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3} + }, {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50, {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK} }, + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51, + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK, + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK} + }, + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK} + }, + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64, + {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK} + }, + {PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, + EXT_CLK_4, SYSTEM_PLL1_400M_CLK} + }, + {PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK} + }, + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}, + }, + {VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69, + {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK} + }, {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0, {DRAM_PLL1_CLK} }, + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0, + {ARM_A53_ALT_CLK, ARM_PLL_CLK} + }, +}; +#elif defined(CONFIG_IMX8MN) +static struct clk_root_map root_array[] = { + {ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0, + {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK} + }, + {ARM_M7_CLK_ROOT, CORE_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK, + VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {GPU_CORE_CLK_ROOT, CORE_CLOCK_SLICE, 3, + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU_SHADER_CLK_ROOT, CORE_CLOCK_SLICE, 4, + {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK} + }, + {ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK} + }, + {NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK} + }, + {DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4, + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_4} + }, + {DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK, + EXT_CLK_1, EXT_CLK_3} + }, + {USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, + {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK} + }, + {DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {DISPLAY_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10, + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3} + }, + {ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4} + }, + {ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4, + VIDEO_PLL_CLK} + }, + {ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21, + {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK} + }, + {NAND_CLK_ROOT, IP_CLOCK_SLICE, 22, + {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK} + }, + {QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK, + SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29, + {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, + AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK} + }, + {UART1_CLK_ROOT, IP_CLOCK_SLICE, 30, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART2_CLK_ROOT, IP_CLOCK_SLICE, 31, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {UART3_CLK_ROOT, IP_CLOCK_SLICE, 32, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {UART4_CLK_ROOT, IP_CLOCK_SLICE, 33, + {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34, + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35, + {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK, + EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {GIC_CLK_ROOT, IP_CLOCK_SLICE, 36, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK, + EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK} + }, + {ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK, + SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2, + SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK} + }, + {GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1} + }, + {GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2} + }, + {GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK, + SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3} + }, + {TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3} + }, + {WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50, + {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK, + VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK} + }, + {WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51, + {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK, + SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK} + }, + {IPP_DO_CLKO1, IP_CLOCK_SLICE, 52, + {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK, + SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK, + SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK} + }, + {IPP_DO_CLKO2, IP_CLOCK_SLICE, 53, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK, + SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK, + AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK} + }, + {MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {DISPLAY_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} + }, + {DISPLAY_CAMERA_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 58, + {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, + {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67, + {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, + SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} + }, + {PDM_CLK_ROOT, IP_CLOCK_SLICE, 68, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}, + }, + {SAI7_CLK_ROOT, IP_CLOCK_SLICE, 70, + {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK, + VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK, + OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4} + }, + {DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0, + {DRAM_PLL1_CLK} + }, + {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0, + {ARM_A53_ALT_CLK, ARM_PLL_CLK} + }, }; #elif defined(CONFIG_IMX8MP) static struct clk_root_map root_array[] = { @@ -580,6 +1325,26 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK} }, + {MEDIA_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4, + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, + AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK} + }, + {MEDIA_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, + AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK} + }, + {HDMI_APB_CLK_ROOT, BUS_CLOCK_SLICE, 6, + {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, + AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL1_133M_CLK} + }, + {HDMI_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 7, + {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, + AUDIO_PLL2_CLK, EXT_CLK_1, SYSTEM_PLL2_500M_CLK} + }, {NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10, {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK, @@ -605,6 +1370,11 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} }, + {MEDIA_DISP2_CLK_ROOT, AHB_CLOCK_SLICE, 3, + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, {DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0, {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK, @@ -615,11 +1385,6 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK} }, - {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 6, - {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, - SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, - SYSTEM_PLL1_133M_CLK} - }, {I2C5_CLK_ROOT, IP_CLOCK_SLICE, 9, {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, @@ -798,11 +1563,36 @@ static struct clk_root_map root_array[] = { SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK} }, + {HDMI_REF_266M_CLK_ROOT, IP_CLOCK_SLICE, 56, + {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK, + SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_266M_CLK, + SYSTEM_PLL2_200M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK} + }, {USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57, {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK} }, + {MEDIA_MIPI_PHY1_REF_CLK_ROOT, IP_CLOCK_SLICE, 59, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MEDIA_DISP1_PIX_CLK_ROOT, IP_CLOCK_SLICE, 60, + {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK, + AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK, + SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4} + }, + {MEDIA_LDB_CLK_ROOT, IP_CLOCK_SLICE, 62, + {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK} + }, + {MEMREPAIR_CLK_ROOT, IP_CLOCK_SLICE, 63, + {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK, + SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK, + SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK} + }, {ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67, {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK, @@ -812,7 +1602,7 @@ static struct clk_root_map root_array[] = { {DRAM_PLL1_CLK} }, {CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0, - {DRAM_PLL1_CLK} + {ARM_A53_ALT_CLK, ARM_PLL_CLK} }, }; #endif diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 7fcbd53..89229da 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -165,7 +165,13 @@ static u32 get_cpu_variant_type(u32 type) u32 value = readl(&fuse->tester4); - if (type == MXC_CPU_IMX8MM) { + if (type == MXC_CPU_IMX8MQ) { + if ((value & 0x3) == 0x2) + return MXC_CPU_IMX8MD; + else if (value & 0x200000) + return MXC_CPU_IMX8MQL; + + } else if (type == MXC_CPU_IMX8MM) { switch (value & 0x3) { case 2: if (value & 0x1c0000) @@ -182,6 +188,23 @@ static u32 get_cpu_variant_type(u32 type) return MXC_CPU_IMX8MML; break; } + } else if (type == MXC_CPU_IMX8MN) { + switch (value & 0x3) { + case 2: + if (value & 0x1000000) + return MXC_CPU_IMX8MNDL; + else + return MXC_CPU_IMX8MND; + case 3: + if (value & 0x1000000) + return MXC_CPU_IMX8MNSL; + else + return MXC_CPU_IMX8MNS; + default: + if (value & 0x1000000) + return MXC_CPU_IMX8MNL; + break; + } } return type; @@ -202,7 +225,7 @@ u32 get_cpu_rev(void) return (MXC_CPU_IMX8MP << 12) | reg; } else if (major_low == 0x42) { /* iMX8MN */ - return (MXC_CPU_IMX8MN << 12) | reg; + type = get_cpu_variant_type(MXC_CPU_IMX8MN); } else if (major_low == 0x41) { type = get_cpu_variant_type(MXC_CPU_IMX8MM); } else { @@ -226,6 +249,8 @@ u32 get_cpu_rev(void) } } } + + type = get_cpu_variant_type(type); } return (type << 12) | reg; @@ -364,16 +389,18 @@ int ft_system_setup(void *blob, bd_t *bd) if (nodeoff < 0) continue; /* Not found, skip it */ - printf("Found %s node\n", nodes_path[i]); + debug("Found %s node\n", nodes_path[i]); rc = fdt_delprop(blob, nodeoff, "cpu-idle-states"); + if (rc == -FDT_ERR_NOTFOUND) + continue; if (rc) { printf("Unable to update property %s:%s, err=%s\n", nodes_path[i], "status", fdt_strerror(rc)); return rc; } - printf("Remove %s:%s\n", nodes_path[i], + debug("Remove %s:%s\n", nodes_path[i], "cpu-idle-states"); } } @@ -382,21 +409,42 @@ int ft_system_setup(void *blob, bd_t *bd) } #endif -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYSRESET) +#if !CONFIG_IS_ENABLED(SYSRESET) void reset_cpu(ulong addr) { - struct watchdog_regs *wdog = (struct watchdog_regs *)addr; + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - if (!addr) - wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + /* Clear WDA to trigger WDOG_B immediately */ + writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr); - /* Clear WDA to trigger WDOG_B immediately */ - writew((WCR_WDE | WCR_SRS), &wdog->wcr); + while (1) { + /* + * spin for .5 seconds before reset + */ + } +} +#endif + +#if defined(CONFIG_ARCH_MISC_INIT) +static void acquire_buildinfo(void) +{ + u64 atf_commit = 0; + + /* Get ARM Trusted Firmware commit id */ + atf_commit = call_imx_sip(IMX_SIP_BUILDINFO, + IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0); + if (atf_commit == 0xffffffff) { + debug("ATF does not support build info\n"); + atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */ + } - while (1) { - /* - * spin for .5 seconds before reset - */ - } + printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit); +} + +int arch_misc_init(void) +{ + acquire_buildinfo(); + + return 0; } #endif diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 49bb3b9..fd3fa04 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -197,52 +197,35 @@ u32 spl_mmc_boot_mode(const u32 boot_device) case SD1_BOOT: case SD2_BOOT: case SD3_BOOT: -#if defined(CONFIG_SPL_FAT_SUPPORT) - return MMCSD_MODE_FS; -#else - return MMCSD_MODE_RAW; -#endif - break; + if (IS_ENABLED(CONFIG_SPL_FS_FAT)) + return MMCSD_MODE_FS; + else + return MMCSD_MODE_RAW; case MMC1_BOOT: case MMC2_BOOT: case MMC3_BOOT: -#if defined(CONFIG_SPL_FAT_SUPPORT) - return MMCSD_MODE_FS; -#elif defined(CONFIG_SUPPORT_EMMC_BOOT) - return MMCSD_MODE_EMMCBOOT; -#else - return MMCSD_MODE_RAW; -#endif - break; + if (IS_ENABLED(CONFIG_SPL_FS_FAT)) + return MMCSD_MODE_FS; + else if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + else + return MMCSD_MODE_RAW; default: puts("spl: ERROR: unsupported device\n"); hang(); } #else -/* - * When CONFIG_SPL_FORCE_MMC_BOOT is defined the 'boot_device' is used - * unconditionally to decide about device to use for booting. - * This is crucial for falcon boot mode, when board boots up (i.e. ROM - * loads SPL) from slow SPI-NOR memory and afterwards the SPL's 'falcon' boot - * mode is used to load Linux OS from eMMC partition. - */ -#ifdef CONFIG_SPL_FORCE_MMC_BOOT switch (boot_device) { -#else - switch (spl_boot_device()) { -#endif /* for MMC return either RAW or FAT mode */ case BOOT_DEVICE_MMC1: case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: -#if defined(CONFIG_SPL_FS_FAT) - return MMCSD_MODE_FS; -#elif defined(CONFIG_SUPPORT_EMMC_BOOT) - return MMCSD_MODE_EMMCBOOT; -#else - return MMCSD_MODE_RAW; -#endif - break; + if (IS_ENABLED(CONFIG_SPL_FS_FAT)) + return MMCSD_MODE_FS; + else if (IS_ENABLED(CONFIG_SUPPORT_EMMC_BOOT)) + return MMCSD_MODE_EMMCBOOT; + else + return MMCSD_MODE_RAW; default: puts("spl: ERROR: unsupported device\n"); hang(); |