treewide: replace with error() with pr_err()

U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>

7 files changed, 25 insertions, 25 deletions

diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c
index cf6626f..dec7d90 100644
--- a/arch/arm/mach-tegra/ivc.c
+++ b/arch/arm/mach-tegra/ivc.c
@@ -493,7 +493,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
 	       (TEGRA_IVC_ALIGN - 1));
 
 	if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) {
-		error("tegra_ivc: nframes * frame_size overflows\n");
+		pr_err("tegra_ivc: nframes * frame_size overflows\n");
 		return -EINVAL;
 	}
 
@@ -503,12 +503,12 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
 	 */
 	if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) ||
 	    (qbase2 & (TEGRA_IVC_ALIGN - 1))) {
-		error("tegra_ivc: channel start not aligned\n");
+		pr_err("tegra_ivc: channel start not aligned\n");
 		return -EINVAL;
 	}
 
 	if (frame_size & (TEGRA_IVC_ALIGN - 1)) {
-		error("tegra_ivc: frame size not adequately aligned\n");
+		pr_err("tegra_ivc: frame size not adequately aligned\n");
 		return -EINVAL;
 	}
 
@@ -521,7 +521,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes,
 	}
 
 	if (ret) {
-		error("tegra_ivc: queue regions overlap\n");
+		pr_err("tegra_ivc: queue regions overlap\n");
 		return ret;
 	}
 
diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
index d326a6a..bfc0ab8 100644
--- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c
@@ -137,7 +137,7 @@ static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
 	u32 value;
 
 	if (padctl->enable == 0) {
-		error("unbalanced enable/disable");
+		pr_err("unbalanced enable/disable");
 		return 0;
 	}
 
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
index 966cf9f..5224ef6 100644
--- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
@@ -45,12 +45,12 @@ int dram_init(void)
 
 	node = fdt_path_offset(nvtboot_blob, "/memory");
 	if (node < 0) {
-		error("Can't find /memory node in nvtboot DTB");
+		pr_err("Can't find /memory node in nvtboot DTB");
 		hang();
 	}
 	prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
 	if (!prop) {
-		error("Can't find /memory/reg property in nvtboot DTB");
+		pr_err("Can't find /memory/reg property in nvtboot DTB");
 		hang();
 	}
 
diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c
index ec04cf5..81fb1d8 100644
--- a/arch/arm/mach-tegra/tegra20/clock.c
+++ b/arch/arm/mach-tegra/tegra20/clock.c
@@ -667,7 +667,7 @@ static int tegra_plle_train(void)
 	} while (--timeout);
 
 	if (timeout == 0) {
-		error("timeout waiting for PLLE to become ready");
+		pr_err("timeout waiting for PLLE to become ready");
 		return -ETIMEDOUT;
 	}
 
@@ -697,7 +697,7 @@ int tegra_plle_enable(void)
 	if ((value & PLLE_MISC_PLL_READY) == 0) {
 		err = tegra_plle_train();
 		if (err < 0) {
-			error("failed to train PLLE: %d", err);
+			pr_err("failed to train PLLE: %d", err);
 			return err;
 		}
 	}
@@ -726,7 +726,7 @@ int tegra_plle_enable(void)
 	} while (--timeout);
 
 	if (timeout == 0) {
-		error("timeout waiting for PLLE to lock");
+		pr_err("timeout waiting for PLLE to lock");
 		return -ETIMEDOUT;
 	}
 
diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
index bf85e07..a3e3e37 100644
--- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c
+++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c
@@ -125,7 +125,7 @@ static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
 	u32 value;
 
 	if (padctl->enable == 0) {
-		error("unbalanced enable/disable");
+		pr_err("unbalanced enable/disable");
 		return 0;
 	}
 
diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c
index 4fd8b8a..282f34f 100644
--- a/arch/arm/mach-tegra/tegra30/clock.c
+++ b/arch/arm/mach-tegra/tegra30/clock.c
@@ -696,7 +696,7 @@ static int tegra_plle_train(void)
 	} while (--timeout);
 
 	if (timeout == 0) {
-		error("timeout waiting for PLLE to become ready");
+		pr_err("timeout waiting for PLLE to become ready");
 		return -ETIMEDOUT;
 	}
 
@@ -726,7 +726,7 @@ int tegra_plle_enable(void)
 	if ((value & PLLE_MISC_PLL_READY) == 0) {
 		err = tegra_plle_train();
 		if (err < 0) {
-			error("failed to train PLLE: %d", err);
+			pr_err("failed to train PLLE: %d", err);
 			return err;
 		}
 	}
@@ -772,7 +772,7 @@ int tegra_plle_enable(void)
 	} while (--timeout);
 
 	if (timeout == 0) {
-		error("timeout waiting for PLLE to lock");
+		pr_err("timeout waiting for PLLE to lock");
 		return -ETIMEDOUT;
 	}
 
diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c
index abc18c0..c8a468a 100644
--- a/arch/arm/mach-tegra/xusb-padctl-common.c
+++ b/arch/arm/mach-tegra/xusb-padctl-common.c
@@ -84,7 +84,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
 
 	len = ofnode_read_string_count(node, "nvidia,lanes");
 	if (len < 0) {
-		error("failed to parse \"nvidia,lanes\" property");
+		pr_err("failed to parse \"nvidia,lanes\" property");
 		return -EINVAL;
 	}
 
@@ -94,7 +94,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
 		ret = ofnode_read_string_index(node, "nvidia,lanes", i,
 					       &group->pins[i]);
 		if (ret) {
-			error("failed to read string from \"nvidia,lanes\" property");
+			pr_err("failed to read string from \"nvidia,lanes\" property");
 			return -EINVAL;
 		}
 	}
@@ -104,7 +104,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl,
 	ret = ofnode_read_string_index(node, "nvidia,function", 0,
 				       &group->func);
 	if (ret) {
-		error("failed to parse \"nvidia,func\" property");
+		pr_err("failed to parse \"nvidia,func\" property");
 		return -EINVAL;
 	}
 
@@ -157,14 +157,14 @@ tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl,
 
 		lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]);
 		if (!lane) {
-			error("no lane for pin %s", group->pins[i]);
+			pr_err("no lane for pin %s", group->pins[i]);
 			continue;
 		}
 
 		func = tegra_xusb_padctl_lane_find_function(padctl, lane,
 							    group->func);
 		if (func < 0) {
-			error("function %s invalid for lane %s: %d",
+			pr_err("function %s invalid for lane %s: %d",
 			      group->func, lane->name, func);
 			continue;
 		}
@@ -206,7 +206,7 @@ tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl,
 
 		err = tegra_xusb_padctl_group_apply(padctl, group);
 		if (err < 0) {
-			error("failed to apply group %s: %d",
+			pr_err("failed to apply group %s: %d",
 			      group->name, err);
 			continue;
 		}
@@ -232,7 +232,7 @@ tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl,
 
 		err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode);
 		if (err < 0) {
-			error("failed to parse group %s", group->name);
+			pr_err("failed to parse group %s", group->name);
 			return err;
 		}
 
@@ -250,7 +250,7 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
 
 	err = ofnode_read_resource(node, 0, &padctl->regs);
 	if (err < 0) {
-		error("registers not found");
+		pr_err("registers not found");
 		return err;
 	}
 
@@ -261,7 +261,7 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl,
 		err = tegra_xusb_padctl_config_parse_dt(padctl, config,
 							subnode);
 		if (err < 0) {
-			error("failed to parse entry %s: %d",
+			pr_err("failed to parse entry %s: %d",
 			      config->name, err);
 			continue;
 		}
@@ -289,7 +289,7 @@ int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
 
 		err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]);
 		if (err < 0) {
-			error("failed to parse DT: %d", err);
+			pr_err("failed to parse DT: %d", err);
 			continue;
 		}
 
@@ -298,7 +298,7 @@ int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count,
 
 		err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config);
 		if (err < 0) {
-			error("failed to apply pinmux: %d", err);
+			pr_err("failed to apply pinmux: %d", err);
 			continue;
 		}