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author | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-07-03 18:06:54 +0300 |
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committer | Svyatoslav Ryhel <clamor95@gmail.com> | 2023-12-19 21:24:11 +0200 |
commit | 1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1 (patch) | |
tree | 927d5d9f7d9908ef42dae037cfdd313d7b1f3f98 /arch/arm/mach-tegra/tegra210/clock.c | |
parent | c03cd98d1a163666b4addcdd9a34fc0c77dfd0a5 (diff) | |
download | u-boot-1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1.zip u-boot-1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1.tar.gz u-boot-1ba80d1b2ce474e0e924bc9c0c1b44d3554204b1.tar.bz2 |
ARM: tegra: clock: support get and set rate for simple PLL
Simple PLL clocks like PLLD2 were omitted since they do not share common
4 register structure with main clocks. Such clocks are containd in simple
PLL group. Only clock_start_pll function supported them. This patch expands
this support on clock_set_rate and clock_get_rate which should make
simple PLL clocks equal to main PLL clocks.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra210/clock.c')
-rw-r--r-- | arch/arm/mach-tegra/tegra210/clock.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c index 900537a..74817e0 100644 --- a/arch/arm/mach-tegra/tegra210/clock.c +++ b/arch/arm/mach-tegra/tegra210/clock.c @@ -1266,6 +1266,21 @@ int tegra_plle_enable(void) return 0; } +struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid) +{ + struct clk_rst_ctlr *clkrst = + (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + + switch (clkid) { + case CLOCK_ID_XCPU: + case CLOCK_ID_EPCI: + case CLOCK_ID_SFROM32KHZ: + return &clkrst->crc_pll_simple[clkid - CLOCK_ID_FIRST_SIMPLE]; + default: + return NULL; + } +} + struct periph_clk_init periph_clk_init_table[] = { { PERIPH_ID_SBC1, CLOCK_ID_PERIPH }, { PERIPH_ID_SBC2, CLOCK_ID_PERIPH }, |