diff options
| author | Jernej Skrabec <jernej.skrabec@siol.net> | 2021-02-01 18:25:57 +0100 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2021-02-19 23:28:50 +0000 |
| commit | bc24884c4c6bb589d61a1802cc0824b00ffe72d1 (patch) | |
| tree | e689b212b1ccc74974c7040577c77b5fead1e04d /arch/arm/mach-sunxi | |
| parent | a1a652e8016426e2d67148cab225cd5ec45189fb (diff) | |
| download | u-boot-bc24884c4c6bb589d61a1802cc0824b00ffe72d1.zip u-boot-bc24884c4c6bb589d61a1802cc0824b00ffe72d1.tar.gz u-boot-bc24884c4c6bb589d61a1802cc0824b00ffe72d1.tar.bz2 | |
sunxi: spl: Fix H616 clock initialization
It turns out that there is a magic bit in PRCM region which seemingly
makes PLLs work if it's enabled. Sadly, there is no documentation what
it does exactly, so we'll just mimick BSP boot0 behaviour and enable it
before any clock is set up.
Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch/arm/mach-sunxi')
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun50i_h6.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 06d84eb..492fc4a 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -9,6 +9,11 @@ void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* this seems to enable PLLs on H616 */ + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10); + clock_set_pll1(408000000); writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); |