From bc24884c4c6bb589d61a1802cc0824b00ffe72d1 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Mon, 1 Feb 2021 18:25:57 +0100 Subject: sunxi: spl: Fix H616 clock initialization It turns out that there is a magic bit in PRCM region which seemingly makes PLLs work if it's enabled. Sadly, there is no documentation what it does exactly, so we'll just mimick BSP boot0 behaviour and enable it before any clock is set up. Fixes: b18bd53d6cde ("sunxi: introduce support for H616 clocks") Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/clock_sun50i_h6.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-sunxi') diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 06d84eb..492fc4a 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -9,6 +9,11 @@ void clock_init_safe(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* this seems to enable PLLs on H616 */ + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + setbits_le32(SUNXI_PRCM_BASE + 0x250, 0x10); + clock_set_pll1(408000000); writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg); -- cgit v1.1