diff options
author | Patrick Delaunay <patrick.delaunay@st.com> | 2020-04-30 16:30:21 +0200 |
---|---|---|
committer | Patrick Delaunay <patrick.delaunay@st.com> | 2020-05-14 09:02:12 +0200 |
commit | dc7e5f190de5ac89fafe3e6212a6167a2b7a36d0 (patch) | |
tree | 7ecbf62873a7a19b8327a392fcd9593b3ab7effb /arch/arm/mach-stm32mp | |
parent | 7e8471cae5c6614c54b9cfae2746d7299bd47a0c (diff) | |
download | u-boot-dc7e5f190de5ac89fafe3e6212a6167a2b7a36d0.zip u-boot-dc7e5f190de5ac89fafe3e6212a6167a2b7a36d0.tar.gz u-boot-dc7e5f190de5ac89fafe3e6212a6167a2b7a36d0.tar.bz2 |
arm: stm32mp: activate data cache on DDR in SPL
Activate cache on DDR to improve the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START
Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'arch/arm/mach-stm32mp')
-rw-r--r-- | arch/arm/mach-stm32mp/spl.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c index 6368db4..b7e7e92 100644 --- a/arch/arm/mach-stm32mp/spl.c +++ b/arch/arm/mach-stm32mp/spl.c @@ -4,6 +4,7 @@ */ #include <common.h> +#include <cpu_func.h> #include <dm.h> #include <hang.h> #include <spl.h> @@ -128,4 +129,22 @@ void board_init_f(ulong dummy) printf("DRAM init failed: %d\n", ret); hang(); } + + /* + * activate cache on DDR only when DDR is fully initialized + * to avoid speculative access and issue in get_ram_size() + */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE, + DCACHE_DEFAULT_OPTION); +} + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); } |