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| author | Marek Vasut <marex@denx.de> | 2023-05-11 21:55:45 +0200 |
|---|---|---|
| committer | Patrice Chotard <patrice.chotard@foss.st.com> | 2023-06-16 11:09:28 +0200 |
| commit | 715e7090381bd0644592d865ba2d4457ab75b869 (patch) | |
| tree | 94ee6f427b9197ec7eaed679df48c4f27d010d4a /arch/arm/mach-stm32mp/include | |
| parent | d3126a32938c2881bb04391480dcb4b8f2529b7b (diff) | |
| download | u-boot-715e7090381bd0644592d865ba2d4457ab75b869.zip u-boot-715e7090381bd0644592d865ba2d4457ab75b869.tar.gz u-boot-715e7090381bd0644592d865ba2d4457ab75b869.tar.bz2 | |
ARM: stm32: Add IWDG handling into PSCI suspend code
In case the IWDG is enabled by either U-Boot or Linux, the IWDG can never
be disabled again. That includes low power states, which means that if the
IWDG is enabled, the SoC would reset itself after a while in suspend via
the IWDG. This is not desired behavior.
It is possible to enable IWDG pre-timeout IRQ which is routed into the EXTI,
and use that IRQ to wake the CPU up before the IWDG timeout is reached and
reset is triggered. This pre-timeout IRQ can be used to reload the WDT and
then suspend the CPU again every once in a while.
Implement this functionality for both IWDG1 and IWDG2 by reading out all
the unmasked IRQs, comparing the list with currently pending IRQs in GICv3:
- If any IRQ is pending and it is NOT IWDG1 or IWDG2 pre-timeout IRQ,
wake up and let OS handle the IRQs
- If IWDG1 or IWDG2 IRQ is pending and no other IRQ is pending,
ping the respective IWDG and suspend again
This does not seem to have any adverse impact on power consumption in suspend.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/include')
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/stm32.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index c85ae6a..1cdc5e3 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -21,8 +21,10 @@ #define STM32_DBGMCU_BASE 0x50081000 #endif #define STM32_FMC2_BASE 0x58002000 +#define STM32_IWDG2_BASE 0x5A002000 #define STM32_DDRCTRL_BASE 0x5A003000 #define STM32_DDRPHYC_BASE 0x5A004000 +#define STM32_IWDG1_BASE 0x5C003000 #define STM32_TZC_BASE 0x5C006000 #define STM32_ETZPC_BASE 0x5C007000 #define STM32_STGEN_BASE 0x5C008000 |