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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2018-03-20 10:54:53 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-04-06 20:45:28 -0400 |
| commit | 08772f6e79af7b5e7ce4a7f230b7d6f69352a8ec (patch) | |
| tree | 88df49b072d10cb7eb43915e74f34565c7995674 /arch/arm/mach-stm32mp/include/mach/stm32.h | |
| parent | 0ed232b15386616d186b67a3689e149581dcf2b7 (diff) | |
| download | u-boot-08772f6e79af7b5e7ce4a7f230b7d6f69352a8ec.zip u-boot-08772f6e79af7b5e7ce4a7f230b7d6f69352a8ec.tar.gz u-boot-08772f6e79af7b5e7ce4a7f230b7d6f69352a8ec.tar.bz2 | |
stm32mp1: get boot mode from BootRom
SPL copy BootRom boot mode information
in TAMP register 21.
This TAMP register information is used
after relocation to set 2 env variables
- boot_device
- boot_instance
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'arch/arm/mach-stm32mp/include/mach/stm32.h')
| -rw-r--r-- | arch/arm/mach-stm32mp/include/mach/stm32.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index ffbe0b1..40faeb0 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -24,4 +24,57 @@ #define STM32_DDR_BASE 0xC0000000 #define STM32_DDR_SIZE SZ_1G +#ifndef __ASSEMBLY__ + +/* + * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT + * - boot device = bit 8:4 + * - boot instance = bit 3:0 + */ +#define BOOT_TYPE_MASK 0xF0 +#define BOOT_TYPE_SHIFT 4 +#define BOOT_INSTANCE_MASK 0x0F +#define BOOT_INSTANCE_SHIFT 0 + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, +}; + +/* TAMP registers */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20) + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) + +#endif /* __ASSEMBLY__*/ #endif /* _MACH_STM32_H_ */ |