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| author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2019-04-09 21:02:05 +0200 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-04-25 00:00:49 +0200 |
| commit | aef44283ac8e4d150f9faa87e16d9b962fc7ef5d (patch) | |
| tree | 689ec5830fb894162c5e4ccfc76626b36d516aa9 /arch/arm/mach-socfpga | |
| parent | 4399e48deb55a5786515e089fe9f0aa6e0ce5d6a (diff) | |
| download | u-boot-aef44283ac8e4d150f9faa87e16d9b962fc7ef5d.zip u-boot-aef44283ac8e4d150f9faa87e16d9b962fc7ef5d.tar.gz u-boot-aef44283ac8e4d150f9faa87e16d9b962fc7ef5d.tar.bz2 | |
arm: socfpga: imply/default common config options
This commit moves common config options used in all socfpga boards
to select/imply in Kconfig. This both cleans up the defconfig files
as well as makes future changes easier.
Options implied/defaulted for all sub-arches:
- SPL, SPL_DM, USE_TINY_PRINTF, NR_DRAM_BANKS
Options implied/defaulted for implied for A10 & gen5:
- FPGA_SOCFPGA, SYS_MALLOC_F_LEN, SYS_TEXT_BASE
Options implied/defaulted for gen5:
- SPL_STACK_R, SPL_SYS_MALLOC_SIMPLE, SPL_STACK_R_ADDR
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/Kconfig | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5e87371..3c6c630 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,8 +1,22 @@ if ARCH_SOCFPGA +config NR_DRAM_BANKS + default 1 + +config SPL_STACK_R_ADDR + default 0x00800000 if TARGET_SOCFPGA_GEN5 + config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 +config SYS_MALLOC_F_LEN + default 0x2000 if TARGET_SOCFPGA_ARRIA10 + default 0x2000 if TARGET_SOCFPGA_GEN5 + +config SYS_TEXT_BASE + default 0x01000040 if TARGET_SOCFPGA_ARRIA10 + default 0x01000040 if TARGET_SOCFPGA_GEN5 + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -21,6 +35,8 @@ config TARGET_SOCFPGA_ARRIA10 select SYSCON select SPL_SYSCON if SPL select ETH_DESIGNWARE_SOCFPGA + imply FPGA_SOCFPGA + imply USE_TINY_PRINTF config TARGET_SOCFPGA_CYCLONE5 bool @@ -29,6 +45,10 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool select ALTERA_SDRAM + imply FPGA_SOCFPGA + imply SPL_STACK_R + imply SPL_SYS_MALLOC_SIMPLE + imply USE_TINY_PRINTF config TARGET_SOCFPGA_STRATIX10 bool |