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| author | Marek Vasut <marex@denx.de> | 2019-02-19 01:11:24 +0100 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-02-25 16:07:36 +0100 |
| commit | 2c0b300bc30881c09519d1f7bfa46a04b0d6d1d5 (patch) | |
| tree | 2591b43f876524012baacc5c6dd732ac581165a9 /arch/arm/mach-socfpga | |
| parent | b275c9aba6d1628211287f80297048128acec964 (diff) | |
| download | u-boot-2c0b300bc30881c09519d1f7bfa46a04b0d6d1d5.zip u-boot-2c0b300bc30881c09519d1f7bfa46a04b0d6d1d5.tar.gz u-boot-2c0b300bc30881c09519d1f7bfa46a04b0d6d1d5.tar.bz2 | |
ARM: socfpga: Configure PL310 latencies
Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/mach-socfpga')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index e1adea1..fcf211d 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | |