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| author | Dinh Nguyen <dinguyen@kernel.org> | 2017-01-31 12:33:08 -0600 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2017-02-08 02:19:11 +0100 |
| commit | a45526aaa0ae241f3e1df996fed988a014eeffe8 (patch) | |
| tree | 7963f647342de91f3fd97aaf6c5cd16ab2916e2e /arch/arm/mach-socfpga/wrap_pll_config.c | |
| parent | c83a824e62277162ad35f52879b2316902c0eff5 (diff) | |
| download | u-boot-a45526aaa0ae241f3e1df996fed988a014eeffe8.zip u-boot-a45526aaa0ae241f3e1df996fed988a014eeffe8.tar.gz u-boot-a45526aaa0ae241f3e1df996fed988a014eeffe8.tar.bz2 | |
arm: socfpga: set the mpuclk divider in the Altera group register
The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.
Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'arch/arm/mach-socfpga/wrap_pll_config.c')
| -rw-r--r-- | arch/arm/mach-socfpga/wrap_pll_config.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 8a0a0e6..72b5f92 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = { CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), + + /* altera group */ + CONFIG_HPS_ALTERAGRP_MPUCLK, }; const struct cm_config * const cm_get_default_config(void) |