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| author | Sumit Garg <sumit.garg@linaro.org> | 2023-02-01 19:28:57 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-02-10 12:50:00 -0500 |
| commit | 22d3fcd337b59808cf90a439e42afeb56da6a54b (patch) | |
| tree | 27ea161524b426d403b4cef92c22f3ca67936bba /arch/arm/mach-snapdragon | |
| parent | de8f42c93a9e714a45f012f87860a8bdaee6cfb9 (diff) | |
| download | u-boot-22d3fcd337b59808cf90a439e42afeb56da6a54b.zip u-boot-22d3fcd337b59808cf90a439e42afeb56da6a54b.tar.gz u-boot-22d3fcd337b59808cf90a439e42afeb56da6a54b.tar.bz2 | |
clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0
Add clk_rcg_set_rate() which allows to configure clocks without programming
MND values. This is required for configuring I2C clocks on QCS404.
Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Diffstat (limited to 'arch/arm/mach-snapdragon')
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-snapdragon.c | 24 | ||||
| -rw-r--r-- | arch/arm/mach-snapdragon/clock-snapdragon.h | 2 |
2 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index fda7098..0ac45dc 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -111,6 +111,30 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, clk_bcr_update(base + regs->cmd_rcgr); } +/* root set rate for clocks with half integer and mnd_width=0 */ +void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, + int source) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + regs->cfg_rcgr); + cfg &= ~CFG_MASK; + cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ + + /* + * Set the divider; HW permits fraction dividers (+0.5), but + * for simplicity, we will support integers only + */ + if (div) + cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; + + writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + + /* Inform h/w to start using the new config. */ + clk_bcr_update(base + regs->cmd_rcgr); +} + static int msm_clk_probe(struct udevice *dev) { struct msm_clk_priv *priv = dev_get_priv(dev); diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 2ac53b5..c90bbef 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -42,5 +42,7 @@ void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source); +void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, + int source); #endif |