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| author | Kever Yang <kever.yang@rock-chips.com> | 2019-07-22 20:01:58 +0800 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2019-07-29 10:25:27 +0800 |
| commit | 604814c8dc5ca56f7103a51d8d209fa26e5ad9ef (patch) | |
| tree | c558683903321dad1eb581e60716b7d4b64d1077 /arch/arm/mach-rockchip/rk3328 | |
| parent | b7abef2ecbcc46df38d5519e649cd3779a17ab35 (diff) | |
| download | u-boot-604814c8dc5ca56f7103a51d8d209fa26e5ad9ef.zip u-boot-604814c8dc5ca56f7103a51d8d209fa26e5ad9ef.tar.gz u-boot-604814c8dc5ca56f7103a51d8d209fa26e5ad9ef.tar.bz2 | |
rockchip: rk3328: add board_debug_uart_init()
Add board_debug_uart_init() to make the debug UART work with
correct setting.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'arch/arm/mach-rockchip/rk3328')
| -rw-r--r-- | arch/arm/mach-rockchip/rk3328/rk3328.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index 222a8d3..afd9de4 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -6,11 +6,17 @@ #include <common.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rk3328.h> +#include <asm/arch-rockchip/uart.h> #include <asm/armv8/mmu.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; +#define CRU_BASE 0xFF440000 +#define GRF_BASE 0xFF100000 +#define UART2_BASE 0xFF130000 + const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "rksdmmc@ff520000", [BROM_BOOTSOURCE_SD] = "rksdmmc@ff500000", @@ -55,3 +61,46 @@ int arch_cpu_init(void) return 0; } + +void board_debug_uart_init(void) +{ + struct rk3328_grf_regs * const grf = (void *)GRF_BASE; + struct rk_uart * const uart = (void *)UART2_BASE; + enum{ + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_UART2_TX_M1 = 1, + + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_UART2_RX_M1 = 1, + }; + enum { + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + }; + + /* uart_sel_clk default select 24MHz */ + writel((3 << (8 + 16)) | (2 << 8), CRU_BASE + 0x148); + + /* init uart baud rate 1500000 */ + writel(0x83, &uart->lcr); + writel(0x1, &uart->rbr); + writel(0x3, &uart->lcr); + + /* Enable early UART2 */ + rk_clrsetreg(&grf->com_iomux, + IOMUX_SEL_UART2_MASK, + IOMUX_SEL_UART2_M1 << IOMUX_SEL_UART2_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A0_SEL_MASK, + GPIO2A0_UART2_TX_M1 << GPIO2A0_SEL_SHIFT); + rk_clrsetreg(&grf->gpio2a_iomux, + GPIO2A1_SEL_MASK, + GPIO2A1_UART2_RX_M1 << GPIO2A1_SEL_SHIFT); + + /* enable FIFO */ + writel(0x1, &uart->sfe); +} |