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author | Tom Rini <trini@konsulko.com> | 2016-11-07 21:34:54 -0500 |
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committer | Tom Rini <trini@konsulko.com> | 2016-11-21 14:07:29 -0500 |
commit | 983e37007da506e8145f9b3a9e1dce5c11116fb0 (patch) | |
tree | c1d5449e1c56e17f22bb4f75b6f11336abca41a4 /arch/arm/mach-omap2/omap3/spl_id_nand.c | |
parent | 272686eb7576c02df4616bcf893fde993e7ba57e (diff) | |
download | u-boot-983e37007da506e8145f9b3a9e1dce5c11116fb0.zip u-boot-983e37007da506e8145f9b3a9e1dce5c11116fb0.tar.gz u-boot-983e37007da506e8145f9b3a9e1dce5c11116fb0.tar.bz2 |
arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-omap2/omap3/spl_id_nand.c')
-rw-r--r-- | arch/arm/mach-omap2/omap3/spl_id_nand.c | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap3/spl_id_nand.c b/arch/arm/mach-omap2/omap3/spl_id_nand.c new file mode 100644 index 0000000..0e2f0a2 --- /dev/null +++ b/arch/arm/mach-omap2/omap3/spl_id_nand.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, <www.ti.com> + * + * Author : + * Tom Rini <trini@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + * Jian Zhang <jzhang@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <jffs2/load_kernel.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/omap_gpmc.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> + +/* + * Many boards will want to know the results of the NAND_CMD_READID command + * in order to decide what to do about DDR initialization. This function + * allows us to do that very early and to pass those results back to the + * board so it can make whatever decisions need to be made. + */ +int identify_nand_chip(int *mfr, int *id) +{ + int loops = 1000; + + /* Make sure that we have setup GPMC for NAND correctly. */ + set_gpmc_cs0(MTD_DEV_TYPE_NAND); + + sdelay(2000); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + sdelay(100); + if (--loops == 0) + return 1; + } + writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); + + /* Set the address to read to 0x0 */ + writeb(0x0, &gpmc_cfg->cs[0].nand_adr); + + /* Read off the manufacturer and device id. */ + *mfr = readb(&gpmc_cfg->cs[0].nand_dat); + *id = readb(&gpmc_cfg->cs[0].nand_dat); + + return 0; +} |