diff options
author | David Huang <d-huang@ti.com> | 2022-01-25 20:56:31 +0530 |
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committer | Tom Rini <trini@konsulko.com> | 2022-02-08 09:41:26 -0500 |
commit | 681023aba4ceb4cb51bcbdc50c41afe8841c2628 (patch) | |
tree | 2bb2b57348f91bda404f469eaf4b20f3afd95751 /arch/arm/mach-k3/include/mach | |
parent | a48fc5cc6f380c048b1edeea548b81dd13ca7320 (diff) | |
download | u-boot-681023aba4ceb4cb51bcbdc50c41afe8841c2628.zip u-boot-681023aba4ceb4cb51bcbdc50c41afe8841c2628.tar.gz u-boot-681023aba4ceb4cb51bcbdc50c41afe8841c2628.tar.bz2 |
arm: K3: Add basic support for J721S2 SoC definition
Add basic support for J721S2 SoC definition
Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Diffstat (limited to 'arch/arm/mach-k3/include/mach')
-rw-r--r-- | arch/arm/mach-k3/include/mach/hardware.h | 4 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/j721s2_hardware.h | 60 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/j721s2_spl.h | 46 | ||||
-rw-r--r-- | arch/arm/mach-k3/include/mach/spl.h | 4 |
4 files changed, 114 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index 8725e7d..5c1265f 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -14,6 +14,10 @@ #include "j721e_hardware.h" #endif +#ifdef CONFIG_SOC_K3_J721S2 +#include "j721s2_hardware.h" +#endif + #ifdef CONFIG_SOC_K3_AM642 #include "am64_hardware.h" #endif diff --git a/arch/arm/mach-k3/include/mach/j721s2_hardware.h b/arch/arm/mach-k3/include/mach/j721s2_hardware.h new file mode 100644 index 0000000..23dfe2e --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j721s2_hardware.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * K3: J721S2 SoC definitions, structures etc. + * + * (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + */ +#ifndef __ASM_ARCH_J721S2_HARDWARE_H +#define __ASM_ARCH_J721S2_HARDWARE_H + +#include <config.h> +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define CTRL_MMR0_BASE 0x00100000 +#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30) + +#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0) +#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0 +#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1) +#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1 +#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6) +#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6 +#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7) +#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7 + +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 + +#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30) +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3) +#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3 +#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6) +#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism + * shared register definitions. + */ +#define CTRLMMR_LOCK_KICK0 0x01008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) +#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 +#define CTRLMMR_LOCK_KICK1 0x0100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + +/* ROM HANDOFF Structure location */ +#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00 + +/* MCU SCRATCHPAD usage */ +#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE + +#endif /* __ASM_ARCH_J721S2_HARDWARE_H */ diff --git a/arch/arm/mach-k3/include/mach/j721s2_spl.h b/arch/arm/mach-k3/include/mach/j721s2_spl.h new file mode 100644 index 0000000..94b6c13 --- /dev/null +++ b/arch/arm/mach-k3/include/mach/j721s2_spl.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ + * David Huang <d-huang@ti.com> + */ +#ifndef _ASM_ARCH_J721S2_SPL_H_ +#define _ASM_ARCH_J721S2_SPL_H_ + +/* With BootMode B = 0 */ +#include <linux/bitops.h> +#define BOOT_DEVICE_HYPERFLASH 0x00 +#define BOOT_DEVICE_OSPI 0x01 +#define BOOT_DEVICE_QSPI 0x02 +#define BOOT_DEVICE_SPI 0x03 +#define BOOT_DEVICE_ETHERNET 0x04 +#define BOOT_DEVICE_I2C 0x06 +#define BOOT_DEVICE_UART 0x07 +#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH + +/* With BootMode B = 1 */ +#define BOOT_DEVICE_MMC2 0x10 +#define BOOT_DEVICE_MMC1 0x11 +#define BOOT_DEVICE_DFU 0x12 +#define BOOT_DEVICE_UFS 0x13 +#define BOOT_DEVIE_GPMC 0x14 +#define BOOT_DEVICE_PCIE 0x15 +#define BOOT_DEVICE_XSPI 0x16 +#define BOOT_DEVICE_RAM 0x17 +#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */ + +/* Backup boot modes with MCU Only = 0 */ +#define BACKUP_BOOT_DEVICE_RAM 0x0 +#define BACKUP_BOOT_DEVICE_USB 0x1 +#define BACKUP_BOOT_DEVICE_UART 0x3 +#define BACKUP_BOOT_DEVICE_ETHERNET 0x4 +#define BACKUP_BOOT_DEVICE_MMC2 0x5 +#define BACKUP_BOOT_DEVICE_SPI 0x6 +#define BACKUP_BOOT_DEVICE_I2C 0x7 + +#define BOOT_MODE_B_SHIFT 4 +#define BOOT_MODE_B_MASK BIT(4) + +#define K3_PRIMARY_BOOTMODE 0x0 +#define K3_BACKUP_BOOTMODE 0x1 + +#endif diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h index ef1c3fb..8a61398 100644 --- a/arch/arm/mach-k3/include/mach/spl.h +++ b/arch/arm/mach-k3/include/mach/spl.h @@ -14,6 +14,10 @@ #include "j721e_spl.h" #endif +#ifdef CONFIG_SOC_K3_J721S2 +#include "j721s2_spl.h" +#endif + #ifdef CONFIG_SOC_K3_AM642 #include "am64_spl.h" #endif |