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| author | Samuel Mescoff <samuel.mescoff@mobile-devices.fr> | 2016-02-16 09:45:06 +0100 |
|---|---|---|
| committer | Andreas Bießmann <andreas.devel@googlemail.com> | 2016-02-18 21:34:41 +0100 |
| commit | f7cf291aa788eb5b64c0d16de529b1a378f509bb (patch) | |
| tree | 7fb741b4c492033d0b5fb364dc372dbb995898b9 /arch/arm/mach-at91/include | |
| parent | c21c28b6f39468dcc13f82458fa3c6f6c5dce9d9 (diff) | |
| download | u-boot-f7cf291aa788eb5b64c0d16de529b1a378f509bb.zip u-boot-f7cf291aa788eb5b64c0d16de529b1a378f509bb.tar.gz u-boot-f7cf291aa788eb5b64c0d16de529b1a378f509bb.tar.bz2 | |
ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Diffstat (limited to 'arch/arm/mach-at91/include')
| -rw-r--r-- | arch/arm/mach-at91/include/mach/at91_common.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-at91/include/mach/sama5_sfr.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index efcd74e..0742ffc 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -34,5 +34,6 @@ void at91_spl_board_init(void); void at91_disable_wdt(void); void matrix_init(void); void redirect_int_from_saic_to_aic(void); +void configure_2nd_sram_as_l2_cache(void); #endif /* AT91_COMMON_H */ diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h b/arch/arm/mach-at91/include/mach/sama5_sfr.h index 7b19a20..b040256 100644 --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h @@ -25,6 +25,7 @@ struct atmel_sfr { u32 sn0; /* 0x4c */ u32 sn1; /* 0x50 */ u32 aicredir; /* 0x54 */ + u32 l2cc_hramc; /* 0x58 */ }; /* Bit field in DDRCFG */ |