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| author | Jernej Skrabec <jernej.skrabec@gmail.com> | 2023-04-10 10:21:13 +0200 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2023-04-12 00:17:21 +0100 |
| commit | f221411caa901cc02ac4aea6a39fa562e87aaa59 (patch) | |
| tree | d9cde6d0e8eef8636236ad37b760e15340c560ec /arch/arm/include | |
| parent | f35ec2105ed8e3c9279e71adc390b83a2c5c1850 (diff) | |
| download | u-boot-f221411caa901cc02ac4aea6a39fa562e87aaa59.zip u-boot-f221411caa901cc02ac4aea6a39fa562e87aaa59.tar.gz u-boot-f221411caa901cc02ac4aea6a39fa562e87aaa59.tar.bz2 | |
sunxi: Convert H616 DRAM options to single setting
Vendor DRAM settings use TPR10 parameter to enable various features.
There are many mores features that just those that are currently
mentioned. Since new will be added later and most are not known, let's
reuse value from vendor DRAM driver as-is. This will also help adding
support for new boards.
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h index c9e1f84..dbdc6b6 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h @@ -137,6 +137,14 @@ check_member(sunxi_mctl_ctl_reg, unk_0x4240, 0x4240); #define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24) #define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) +#define TPR10_CA_BIT_DELAY BIT(16) +#define TPR10_DX_BIT_DELAY0 BIT(17) +#define TPR10_DX_BIT_DELAY1 BIT(18) +#define TPR10_WRITE_LEVELING BIT(20) +#define TPR10_READ_CALIBRATION BIT(21) +#define TPR10_READ_TRAINING BIT(22) +#define TPR10_WRITE_TRAINING BIT(23) + struct dram_para { u32 clk; enum sunxi_dram_type type; @@ -147,6 +155,7 @@ struct dram_para { u32 dx_odt; u32 dx_dri; u32 ca_dri; + u32 tpr10; }; |