arch-stm32: Factorize stm32.h for STM32F4 and F7

For STM32F4 and F7 SoCx family, a specific stm32.h file exists.
Some common defines are duplicated or even unused in each of
these stm32.h.

Factorize all common definition in arch/arm/include/asm/stm32f.h and keep
specific definitions in each arch/arm/include/asm/arch-stm32fx/stm32.h.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

3 files changed, 25 insertions, 56 deletions

diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h
new file mode 100644
index 0000000..7bea20b
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32/stm32f.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_STM32F_H
+#define _ASM_ARCH_STM32F_H
+
+#define STM32_PERIPH_BASE	0x40000000UL
+
+#define STM32_APB2_PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1_PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
+
+#define STM32_SYSCFG_BASE	(STM32_APB2_PERIPH_BASE + 0x3800)
+#define STM32_FLASH_CNTL_BASE	(STM32_AHB1_PERIPH_BASE + 0x3C00)
+
+void stm32_flash_latency_cfg(int latency);
+
+#endif /* _ASM_ARCH_STM32F_H */
+
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
index 763b18c..9039312 100644
--- a/arch/arm/include/asm/arch-stm32f4/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -11,17 +11,12 @@
 #ifndef _MACH_STM32_H_
 #define _MACH_STM32_H_
 
+#include <asm/arch-stm32/stm32f.h>
+
 /*
  * Peripheral memory map
  */
 #define STM32_SYSMEM_BASE	0x1FFF0000
-#define STM32_PERIPH_BASE	0x40000000
-#define STM32_APB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00000000)
-#define STM32_APB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
-#define STM32_AHB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
-#define STM32_AHB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x10000000)
-
-#define STM32_BUS_MASK		0xFFFF0000
 
 /*
  * Register maps
@@ -37,15 +32,10 @@ struct stm32_u_id_regs {
  */
 #define STM32_U_ID_BASE		(STM32_SYSMEM_BASE + 0x7A10)
 #define STM32_U_ID		((struct stm32_u_id_regs *)STM32_U_ID_BASE)
-
-#define FLASH_CNTL_BASE		(STM32_AHB1PERIPH_BASE + 0x3C00)
-
 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
 	[0 ... 3] =	16 * 1024,
 	[4] =		64 * 1024,
 	[5 ... 11] =	128 * 1024
 };
 
-void stm32_flash_latency_cfg(int latency);
-
 #endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
index 40df891..c1f1ba2 100644
--- a/arch/arm/include/asm/arch-stm32f7/stm32.h
+++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
@@ -8,46 +8,7 @@
 #ifndef _ASM_ARCH_HARDWARE_H
 #define _ASM_ARCH_HARDWARE_H
 
-/* STM32F746 */
-#define ITCM_FLASH_BASE		0x00200000UL
-#define AXIM_FLASH_BASE		0x08000000UL
-
-#define ITCM_SRAM_BASE		0x00000000UL
-#define DTCM_SRAM_BASE		0x20000000UL
-#define SRAM1_BASE		0x20010000UL
-#define SRAM2_BASE		0x2004C000UL
-
-#define PERIPH_BASE		0x40000000UL
-
-#define APB1_PERIPH_BASE	(PERIPH_BASE + 0x00000000)
-#define APB2_PERIPH_BASE	(PERIPH_BASE + 0x00010000)
-#define AHB1_PERIPH_BASE	(PERIPH_BASE + 0x00020000)
-#define AHB2_PERIPH_BASE	(PERIPH_BASE + 0x10000000)
-#define AHB3_PERIPH_BASE	(PERIPH_BASE + 0x20000000)
-
-#define USART2_BASE		(APB1_PERIPH_BASE + 0x4400)
-#define USART3_BASE		(APB1_PERIPH_BASE + 0x4800)
-#define PWR_BASE		(APB1_PERIPH_BASE + 0x7000)
-
-#define USART1_BASE		(APB2_PERIPH_BASE + 0x1000)
-#define USART6_BASE		(APB2_PERIPH_BASE + 0x1400)
-#define STM32_SYSCFG_BASE	(APB2_PERIPH_BASE + 0x3800)
-
-#define STM32_GPIOA_BASE	(AHB1_PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE	(AHB1_PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE	(AHB1_PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE	(AHB1_PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE	(AHB1_PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE	(AHB1_PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE	(AHB1_PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE	(AHB1_PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE	(AHB1_PERIPH_BASE + 0x2000)
-#define STM32_GPIOJ_BASE	(AHB1_PERIPH_BASE + 0x2400)
-#define STM32_GPIOK_BASE	(AHB1_PERIPH_BASE + 0x2800)
-#define FLASH_CNTL_BASE		(AHB1_PERIPH_BASE + 0x3C00)
-
-
-#define SDRAM_FMC_BASE		(AHB3_PERIPH_BASE + 0x40000140)
+#include <asm/arch-stm32/stm32f.h>
 
 static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
 	[0 ... 3] =	32 * 1024,
@@ -55,8 +16,4 @@ static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
 	[5 ... 7] =	256 * 1024
 };
 
-#define STM32_BUS_MASK		GENMASK(31, 16)
-
-void stm32_flash_latency_cfg(int latency);
-
 #endif /* _ASM_ARCH_HARDWARE_H */