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| author | Peng Fan <van.freenix@gmail.com> | 2016-08-11 14:02:51 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2016-10-04 15:41:01 +0200 |
| commit | 07e1c0ae83faff57477392be87734128db5e1b14 (patch) | |
| tree | 84d433be88cbd55b97ca541a199eed599ea57435 /arch/arm/imx-common | |
| parent | 5b66482d44b4e9571c64285254a43bdfe9ed1262 (diff) | |
| download | u-boot-07e1c0ae83faff57477392be87734128db5e1b14.zip u-boot-07e1c0ae83faff57477392be87734128db5e1b14.tar.gz u-boot-07e1c0ae83faff57477392be87734128db5e1b14.tar.bz2 | |
imx: iomux: fix snvs usage for i.MX6ULL
SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module,
not in IOMUXC, so correct the related registers' offset.
Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate
them from iomuxc pins.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com>
Diffstat (limited to 'arch/arm/imx-common')
| -rw-r--r-- | arch/arm/imx-common/iomux-v3.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 2612e09..392f4bc 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -42,6 +42,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #ifdef CONFIG_IOMUX_LPSR u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT; +#ifdef CONFIG_MX7 if (lpsr == IOMUX_CONFIG_LPSR) { base = (void *)IOMUXC_LPSR_BASE_ADDR; mux_mode &= ~IOMUX_CONFIG_LPSR; @@ -49,9 +50,17 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; } +#else + if (is_mx6ull()) { + if (lpsr == IOMUX_CONFIG_LPSR) { + base = (void *)IOMUXC_SNVS_BASE_ADDR; + mux_mode &= ~IOMUX_CONFIG_LPSR; + } + } +#endif #endif - if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs) + if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); if (sel_input_ofs) |