From 07e1c0ae83faff57477392be87734128db5e1b14 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 11 Aug 2016 14:02:51 +0800 Subject: imx: iomux: fix snvs usage for i.MX6ULL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SNVS TAMPER pin and BOOT MODE pins are in SNVS IOMUXC module, not in IOMUXC, so correct the related registers' offset. Use IOMUX_CONFIG_LPSR flag for these pins, so we can differentiate them from iomuxc pins. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: "Benoît Thébaudeau" --- arch/arm/imx-common/iomux-v3.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm/imx-common') diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 2612e09..392f4bc 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -42,6 +42,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #ifdef CONFIG_IOMUX_LPSR u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT; +#ifdef CONFIG_MX7 if (lpsr == IOMUX_CONFIG_LPSR) { base = (void *)IOMUXC_LPSR_BASE_ADDR; mux_mode &= ~IOMUX_CONFIG_LPSR; @@ -49,9 +50,17 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; } +#else + if (is_mx6ull()) { + if (lpsr == IOMUX_CONFIG_LPSR) { + base = (void *)IOMUXC_SNVS_BASE_ADDR; + mux_mode &= ~IOMUX_CONFIG_LPSR; + } + } +#endif #endif - if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs) + if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); if (sel_input_ofs) -- cgit v1.1