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| author | Michael Walle <michael@walle.cc> | 2022-02-28 13:48:40 +0100 |
|---|---|---|
| committer | Priyanka Jain <priyanka.jain@nxp.com> | 2022-04-26 17:13:57 +0530 |
| commit | 49bb245f1dc447152a80b522cce7b964e0972517 (patch) | |
| tree | e850791ddd4dc01437a4fe93d565dd76a013b059 /arch/arm/cpu/armv8/Kconfig | |
| parent | de58ac49a5d941a053008bf395c862efc34b5595 (diff) | |
| download | u-boot-49bb245f1dc447152a80b522cce7b964e0972517.zip u-boot-49bb245f1dc447152a80b522cce7b964e0972517.tar.gz u-boot-49bb245f1dc447152a80b522cce7b964e0972517.tar.bz2 | |
armv8: psci: add ARMV8_PSCI_RELOCATE Kconfig option
There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the
same meaning but is just for the ls1043ardb board. As no in-tree config
uses this, drop it and replace it with something more sophiticated:
ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE
option which is used as the base to relocate the PSCI code (or any code
in the secure region, but that is only PSCI). A SoC (or board) can now
opt-in into having such a secure region by enabling
SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was
possible to relocate the PSCI code before as well as on the LS1028A SoC
where there will be PSCI support soon.
Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive.
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/Kconfig')
| -rw-r--r-- | arch/arm/cpu/armv8/Kconfig | 30 |
1 files changed, 19 insertions, 11 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 4d4469c..09f3f50 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -90,6 +90,7 @@ config SPL_RECOVER_DATA_SECTION config SEC_FIRMWARE_ARMV8_PSCI bool "PSCI implementation in secure monitor firmware" depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT + depends on ARMV8_PSCI=n help This config enables the ARMv8 PSCI implementation in secure monitor firmware. This is a private PSCI implementation and different from @@ -131,6 +132,9 @@ config PSCI_RESET Select Y here to make use of PSCI calls for system reset +config SYS_HAS_ARMV8_SECURE_BASE + bool + config ARMV8_PSCI bool "Enable PSCI support" if EXPERT help @@ -158,23 +162,27 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER A value 0 or no definition of it works for single cluster system. System with multi-cluster should difine their own exact value. -config ARMV8_EA_EL3_FIRST - bool "External aborts and SError interrupt exception are taken in EL3" +config ARMV8_PSCI_RELOCATE + bool "Relocate PSCI code" + depends on ARMV8_PSCI + depends on SYS_HAS_ARMV8_SECURE_BASE help - Exception handling at all exception levels for External Abort and - SError interrupt exception are taken in EL3. - -if SYS_HAS_ARMV8_SECURE_BASE + Relocate PSCI code, for example to a secure memory on the SoC. If not + set, the PSCI sections are placed together with the u-boot and the + regions will be marked as reserved before linux is started. config ARMV8_SECURE_BASE hex "Secure address for PSCI image" - depends on ARMV8_PSCI + depends on ARMV8_PSCI_RELOCATE + default 0x18000000 if ARCH_LS1028A help Address for placing the PSCI text, data and stack sections. - If not defined, the PSCI sections are placed together with the u-boot - but platform can choose to place PSCI code image separately in other - places such as some secure RAM built-in SOC etc. -endif + +config ARMV8_EA_EL3_FIRST + bool "External aborts and SError interrupt exception are taken in EL3" + help + Exception handling at all exception levels for External Abort and + SError interrupt exception are taken in EL3. endif |