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| author | Alexey Brodkin <abrodkin@synopsys.com> | 2018-02-21 12:58:00 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2018-03-21 16:21:34 +0300 |
| commit | 71621525c3bf9ed2a73446ba505ad5b980b6b8bb (patch) | |
| tree | 1309125801fb453076652c375beb729950f18b5d /arch/arc | |
| parent | 264d298fda39c5caa9505702b257a1f60c3b7352 (diff) | |
| download | u-boot-71621525c3bf9ed2a73446ba505ad5b980b6b8bb.zip u-boot-71621525c3bf9ed2a73446ba505ad5b980b6b8bb.tar.gz u-boot-71621525c3bf9ed2a73446ba505ad5b980b6b8bb.tar.bz2 | |
arc: Fine-tune implementation of memory barriers
We improve on 2 things:
1. Only ARC HS family has "dmb" instructions so do compile-time
check for automatically defined macro __ARCHS__.
Previous check for ARCv2 ISA was not good enough because ARC EM
family is v2 ISA as well but still "dmb" instaruction is not
supported in EM family.
2. Still if there's no dedicated instruction for memory barrier
let's at least insert compile-time barrier to make sure
compiler deosn't reorder critical memory operations.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/include/asm/io.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index a12303b..060cdf6 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -10,7 +10,7 @@ #include <linux/types.h> #include <asm/byteorder.h> -#ifdef CONFIG_ISA_ARCV2 +#ifdef __ARCHS__ /* * ARCv2 based HS38 cores are in-order issue, but still weakly ordered @@ -42,12 +42,12 @@ #define mb() asm volatile("sync\n" : : : "memory") #endif -#ifdef CONFIG_ISA_ARCV2 +#ifdef __ARCHS__ #define __iormb() rmb() #define __iowmb() wmb() #else -#define __iormb() do { } while (0) -#define __iowmb() do { } while (0) +#define __iormb() asm volatile("" : : : "memory") +#define __iowmb() asm volatile("" : : : "memory") #endif static inline void sync(void) |