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| author | Tom Rini <trini@konsulko.com> | 2022-07-23 13:05:09 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-04 16:18:48 -0400 |
| commit | 923a855509c6114b044b6358c98f1857f52ab80b (patch) | |
| tree | 91b5b089f9fe005a1356f63f432ef548bb89a873 /README | |
| parent | 6f6b9703d0149b784cce81996773e4b84323c7e1 (diff) | |
| download | u-boot-923a855509c6114b044b6358c98f1857f52ab80b.zip u-boot-923a855509c6114b044b6358c98f1857f52ab80b.tar.gz u-boot-923a855509c6114b044b6358c98f1857f52ab80b.tar.bz2 | |
Convert CONFIG_SYS_FSL_CCSR_GUR_BE et al to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FSL_CCSR_GUR_BE
CONFIG_SYS_FSL_CCSR_SCFG_BE
CONFIG_SYS_FSL_ESDHC_BE
CONFIG_SYS_FSL_IFC_BE
CONFIG_SYS_FSL_PEX_LUT_BE
CONFIG_SYS_FSL_CCSR_GUR_LE
CONFIG_SYS_FSL_CCSR_SCFG_LE
CONFIG_SYS_FSL_ESDHC_LE
CONFIG_SYS_FSL_IFC_LE
CONFIG_SYS_FSL_PEX_LUT_LE
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 0 insertions, 6 deletions
@@ -396,12 +396,6 @@ The following options need to be configured: Board config to use DDR3L. It can be enabled for SoCs with DDR3L controllers. - CONFIG_SYS_FSL_IFC_BE - Defines the IFC controller register space as Big Endian - - CONFIG_SYS_FSL_IFC_LE - Defines the IFC controller register space as Little Endian - CONFIG_SYS_FSL_IFC_CLK_DIV Defines divider of platform clock(clock input to IFC controller). |