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| author | Heiko Schocher <hs@denx.de> | 2014-07-18 06:07:21 +0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-07-23 12:26:45 +0200 |
| commit | 562f8df18da62ae02c4ace1e530451fe82c3312d (patch) | |
| tree | f3ac604fb5cc1a3865a91a99763f3d855c19bd4f /README | |
| parent | a0ae0091d783b1140f8d321d8c6d221aeb0d39d0 (diff) | |
| download | u-boot-562f8df18da62ae02c4ace1e530451fe82c3312d.zip u-boot-562f8df18da62ae02c4ace1e530451fe82c3312d.tar.gz u-boot-562f8df18da62ae02c4ace1e530451fe82c3312d.tar.bz2 | |
spi: add config option to enable the WP pin function on st micron flashes
enable the W#/Vpp signal to disable writing to the status
register on ST MICRON flashes like the N25Q128 thorugh
the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'README')
| -rw-r--r-- | README | 11 |
1 files changed, 11 insertions, 0 deletions
@@ -2930,6 +2930,17 @@ CBFS (Coreboot Filesystem) support memories can be connected with a given cs line. currently Xilinx Zynq qspi support these type of connections. + CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + enable the W#/Vpp signal to disable writing to the status + register on ST MICRON flashes like the N25Q128. + The status register write enable/disable bit, combined with + the W#/VPP signal provides hardware data protection for the + device as follows: When the enable/disable bit is set to 1, + and the W#/VPP signal is driven LOW, the status register + nonvolatile bits become read-only and the WRITE STATUS REGISTER + operation will not execute. The only way to exit this + hardware-protected mode is to drive W#/VPP HIGH. + - SystemACE Support: CONFIG_SYSTEMACE |