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| author | Michal Simek <michal.simek@amd.com> | 2023-10-12 14:58:47 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2023-11-07 13:47:09 +0100 |
| commit | f87696afa03db147997bd12efacb7f0ded2ff963 (patch) | |
| tree | db8d6e024fda2f87b6764621305803ccb7df16b4 | |
| parent | 971a77262473fcdccbf77d616c738ec20d32d7a4 (diff) | |
| download | u-boot-f87696afa03db147997bd12efacb7f0ded2ff963.zip u-boot-f87696afa03db147997bd12efacb7f0ded2ff963.tar.gz u-boot-f87696afa03db147997bd12efacb7f0ded2ff963.tar.bz2 | |
arm64: zynqmp: Use mdio node by vp-x-a2785-00-revA and vpk120-revA
All boards have been converted to use mdio node that's why move ethernet
phys under mdio node too.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/6c60f5d29b9d9992bd0130fd263c8ed13cb8166c.1697115523.git.michal.simek@amd.com
| -rw-r--r-- | arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts | 10 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-vpk120-revA.dts | 10 |
2 files changed, 14 insertions, 6 deletions
diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index 2f88aa4..9ab8f5b 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -119,9 +119,13 @@ phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { /* u131 - M88e1512 */ - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { /* u131 - M88e1512 */ + reg = <0>; + }; }; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index 66919f5..ce76e0b 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -120,9 +120,13 @@ phy-mode = "sgmii"; /* DTG generates this properly 1512 */ is-internal-pcspma; /* phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; */ - /* phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ - phy0: ethernet-phy@0 { - reg = <0>; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + /* reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>; */ + phy0: ethernet-phy@0 { + reg = <0>; + }; }; }; |